Power Intent and Standards

Details

Last Updated: Wednesday, 10 February 2021 06:37

Published: Thursday, 04 February 2021 01:29

Hits: 787

Power Intent:

If you recall RTL coding in any HDL language, there is no way to model power connections in RTL. HDL langauges never had power definitions in them. Earlier in 1980's when HDL were being developed, all chips had single power, so there was no need to specify power connections at RTL level. These power connections to std cells were done in physical implementation phase, by the tools. It was very easy to do these, as power lines, VDD and VSS would just connect to power ports of std cells. The power grid for VDD, VSS would finally come to the pads of chip as ppower pins.

Earlier, power was not a concern, so power specific cmds in HDL were never considered. However, now power is a big concern, and a lot of effort goes into reducing power. This involves reducing lkg power of chip, by turning off portions of chip when not in use. Also, multiple voltage supply rails are being used, whose voltage range is dynamic. This asks for putting power definition in RTL to specify what logic is connected to what power supply. However, putting power connections in RTL reduces flexibility of RTL modeling, as it's supposed to focus more on functional aspect. So, standards were developed, which is a separate file with power intent of RTL coded in it, in a syntax called as power formats (PF). This PF file doesn't modify the RTL, but instead adds an abtract layer that defines how various code in RTL are connected to power supply. Simulation tools understand these PF, and simuate design with both RTL and PF in tandem. This is known as "power aware RTL sim" (PARTL Sim). These tools will thrown out an "x" from RTL code, when power supply to that piece of RTL code is OFF.  Thus it allows us to verify our design much before it goes thru physical implememtation. Also, Synthesis/Layout tools can also read this PF file and can know what piece of logic connects to what power supply. That keeps power supply connections easy and automated.

The netlist generated by synthesis/pnr tools can be non PG netlist (netlist which has no power ports for stdcells and modules), or PG netlist (one which has power ports VDD/VSS for stdcells and modules). We can specify what kind of netlist we want generated using options when writing netlist. When we had single power designs, PG netlists were not important as they all connected to single power supply, and didn't provide any extra info. However, now with advent of PF, we more commonly generate PG netlist, which shows power connections to each and every stdcell/macro. This allows us to run power aware simulations on gate level netlist (PAGLS sims). This extra sim allows us to find out if all power connections speciifed in PF file, were indeed done as intended. This sim doesn't need PF file, as all power connections are there in gate level netlist. 

Power Standards:

There are 2 PF standards in use today:

1. UPF (Unified Power format): The IEEE 1801 Unified Power Format (UPF) Standard establishes a set of commands used to specify the low-power design intent for electronic systems.

UPF manual can be downloaded from IEEE website. Std started developing in 2009. Current one is IEEE Std 1801-2017

See Design Compiler guide (Page 154) section 6-18 (specifying power intent) for details.

2. CPF: (Common Power format): This Format was introduced by Cadence, but shortly thereafter, UPF was proposed. Since UPF hasd backing of lot more companies, it was chosen as IEEE std, and CPF became less popular. The technical differences between the two formats are relatively minor. CPF is not really needed anymore as all tools support UPF now. I've a section on CPF, but it's for my reference only. You can omit it completely.

Terminology used in UPF/CPF:

Using UPF/CPF commands, you can specify the supply network, switches, isolation, retention, and other aspects relevant to power management of a chip design.

Power management (PM):  Power management enables a system to operate correctly in a given functional mode with the minimum power consumption. Implementation of pwr mgmt strategies require PM cells as level shifter, isolation, retention reg and repeaters to ensure that the design works correctly in the presence of diff pwr domains. PM cells may have single set of supply (i.e iso cell in destination PD), dual set of supply (i.e iso cell in source PD, level shifter, retention flops, pwr switch) or even more. Objects supplying pwr can be in various supply states, while objects consuming pwr can be in various power states. Supply state of supply port, supply net or supply set function is a combo of 2 values: state value (which may be OFF, UNDETERMINED, PARTIAL_ON and FULL_ON), and a voltage value (value in uV). Powr states are various legal states that objects can be in. These objects may be supply nets/ports/sets, PD, etc.

Below we briefly define various terms used in PM. We'll cover in more detail in UPF section. The terminology I've below is written for UPF, but applies to CPF as well.

1. Power domain:  It's defined group of elements in the logic hierarchy that share a common set of power supply needs. By default, all logic elements in a power domain use the same primary supply and primary ground, and may share other auxillary supplies such as isolation and retention supplies (explained later). A power domain may be single instance or collection of instances, powered by same supply. We define power domains in UPF to identify separate power regions in RTL. power domain identifies the uppermost inst of the domain. Every instance in design should be part of some power domain.

2. scope and extent: Each power domain has a scope and an extent. The scope is the level of logic hierarchy where the power domain exists. Scope in HDL refers to "region of HDL text where names may be defined".  Usually scope is module, submodule or blocks of statement, which can all be nested. Scope in UPF means the same. The extent is the set of logic elements that belong to the power domain and share the same power supply needs. In other words, the scope is the hierarchical level (instance of a module) where the power domain exists, whereas the extent is what all logic is contained within the power domain. So, with "set_scope" cmd, we specify which module of RTL the UPF file applies to. The scope in UPF is set to top module of RTL. If we want UPF file to be applied to some submodule in RTL, we have to set scope accordingly. Extent allows us to omit/include things within that scope that are prsent or absent in that power domain (i.e may be a set of logic within a submodule is supposed to be connected to some other power supply, in this case extent allows us to omit this from this power domain). Otherwise by default, power domain connects everything that is contained in that design hier to that supply to which that power domain is connected to.

Other way to define scope/extent is this: The instance in the logic hierarchy in which a power domain is defined is called the scope of the power domain. The set of instances that belong to a power domain are said to be the extent of that power domain. This distinction is important: while a given instance can be the scope of multiple power domains (i.e 1 power domain may be nested inside other power domain), it can be in the extent of one and only one power domain (since cell power suplly can only be connected to unique pwr supply, i.e VDD pin of cell can't be connected to 2 pwr supply pins). As a consequence of these definitions, all instances within the extent of a domain are necessarily within the scope of the domain or its descendants

3. nets and ports: Each scope or hierarchical level in the design has supply nets and supply ports. A supply net is a conductor that carries a supply voltage or ground throughout a given power domain. A supply port is a power supply connection point between two adjacent levels of the design hierarchy, between parent and child blocks of the hierarchy. We define supply nets and ports in UPF for power signals, even though these power signal nets/ports are absent in RTL. That is how UPF is able to define power intent of design. For macros or power management cells, these power ports may be specified in liberty or thru 'create_supply_port" upf cmds.

Supply net originates at a root supply driver, which can be an on-chip voltage regulator, an embedded power switch, a bias generator, or an off-chip supply source. One or more of these supply nets connect to a power switch, which has single output supply port. Supply network objects are created independent of power-domain definitions. This allows sharing of common components of the supply distribution network across multiple power domains.

4. Supply set: Related supply nets can be grouped into a supply set, with each supply net in the group providing one or more functions of the supply set. In other words, a supply set represents a collection of supply nets that provide a complete power source for one or more instances. Each supply set defines six standard functions: power, ground, pwell, nwell, deeppwell, and deepnwell. Each function represents a potential supply net connection to a corresponding portion of a transistor. Each function of a given supply set can be associated with a particular supply net that implements the function.

Mostly, power and ground are the only 2 supply nets that are needed (as pwell and nwell connections are tied internally to power/ground). Supply functions of a supply set, and the supply nets they represent, can be connected to instances in one of the following ways: explicitly, automatically, or implicitly. Connections are made downward, from ports or nets in the current scope to ports of descendant instances that are in the extent of the domain.

Supply sets may be primary, retention, isolation or level shifter supply sets, depending on what kind of cell they are meant for.

Supply Set Connections: Supply functions of a supply set, and the supply nets they represent, can be connected to instances in one of the following ways: explicitly, automatically, or implicitly. Connections are made downward, from ports or nets in the current scope to ports of descendant instances that are in the extent of the domain.

1. explicit connection:
2. automatic connection: In liberty file, each port has a pg_type as primary power, primary_ground, pwell, nwell, deeppwell, deepnwell. These are connected with matching function names in supply set
3. Implicit connection: An implicit connection connects the required functions of a supply set to cell instances that do not have explicit supply ports.

5. Supply variation: Supply ports, supply nets, and supply set functions take on values that consist of a state and a voltage. Named port states (see 6.4) and named power states (see 6.5) can be defined to represent the nominal voltages that a supply object may carry. These nominal voltage values are used also for determining whether level-shifting is required (see 6.45). In an implementation, the actual voltage of an object may vary around the nominal values. There are several sources of such variation. One source of variation is the accuracy of the supply. Supply variation can be modeled in UPF using the set_variation command (see 6.53). Supply variation is applied to nominal voltages to derive variation ranges for those voltages. Supply variation ranges (see 4.5.7) are used when determining whether level-shifting is needed.

6. Power states: As explained above, power states represent various operational modes of the domain's supply set. As an ex, a power domain may have 3 states: RUNNING, SLEEP and SHUTDOWN. In RUNNING, all supply sets may be at optimal voltage, while in SLEEPING, they might be at reduced voltages. In SHUTDOWN, primary supply may be OFF, while retention and isolation supplies may be ON). A value of 0 or L in HDL is considered ON or FULL_ON, while a value of 1 or H in HDL is considered OFF. X or Z may be considered UNDETERMINED or PARTIAL_ON depending on settings.

7. power switch: A power switch (or simply switch) is a device that turns on and turns off power for a supply net. A switch has an input supply net, an output supply net that can be switched on or off, and at least one input signal to control switching.

Supply network objects (supply ports, supply nets, and switches) are created within the logic hierarchy to provide connection points for a root supply and to propagate the value of a root supply throughout a portion of the design.

8. level shifter: Where a logic signal leaves one power domain and enters another at a substantially different supply voltage, a level-shifter cell must be present to convert the signal from the voltage swing of the first domain to that of the second domain.

9. isolation cell (aka clamp cell): Where a logic signal leaves a power domain and enters a different power domain, an isolation cell must be present to generate a known logic value during shutdown. If the voltage levels of the two domains are substantially different, the interface cell must perform both level shifting when the domain is powered up and isolation when the domain is powered down. A cell that can perform both functions is called an enable level shifter. Tools can optimize away redundant insertion of iso cells (i.e when nets are tied to constant logic, etc)

Isolation may be inserted for an input or for an output of the power domain. It's placed at i/p so that values coming into the power domain are deterministic even when the driver is powered down. They are needed at o/p so that values coming out of this power domain and going into other domain are deterministic even when driver is powered down. If we think about it, we may infer that isolation cells may need to be provided at i/p ports only, since o/p of a port may fan out to different with different clamp value requirements, so providing iso cells at all i/p ports only may work out. However, if we don't provide iso cells at o/p, then the "unknown" values will be going thru nets to all other blocks. These nets will need repeaters to carry the signal, and unknown inputs may cause short circuit current thru repeaters. So, we provide iso cells at both i/p and o/p of all blocks. Isolation cell's power supply for i/p ports is from same PD supply which is consuming it (as isolation is relevant only when the supply for that PD is on). However, this may be an issue for o/p ports, as they will become floating if driven by same power supply. So, we prefer to drive o/p ports with always on power supply, so that we are guaranteed valid iso values all the time??

An isolation cell operates in two modes: normal mode, in which it acts like a buffer, and isolation mode, in which it clamps its output to a defined value. An isolation enable signal determines the operational mode of an isolation cell at any given time.

9. retention reg/flops and memories: In a power domain that has power switching, any registers that are to retain data during shutdown must be implemented as retention registers. A retention register has a separate, always-on supply net, sometimes called the backup supply, which keeps the data stable in while the primary supply of the domain is shut down. Retention capability can be implemented for both registers and memories.

There are 2 flavors of retention reg:

1. Balloon-style retention: In a balloon-style retention register, the retained value is held in an additional latch, often called the balloon latch. In this case, the balloon element is not in the functional data-path of the register.Extra save/restore ports are needed to save or restore the values.
2. Master/slave-alive retention: In a master/slave-alive retention register, the retained value is held in the master or slave latch. In this case, the retention element is in the functional data-path of the register. This style of registers does not have save/restore ports, but may specify a retention condition that could take the register in and out of retention (i.e when power supply turned on/off).

10. Repeaters: Required when distance b/w driver and receiver is large. These repeaters should be on appr power domain.