eco
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- Last Updated: Friday, 19 June 2020 05:34
- Published: Friday, 19 June 2020 03:39
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ECO = Engineering Change Order
ECO is a common term used in Engineering. It refers to documentation process for any design changes made to an existing design to fix a bug. These design changes are usually small, so we make localized changes and document these. It's used in vlsi a lot, since early chips mostly have design bugs, which can only be fixed by making changes to the design. The issue is identified, fix proposed, then it's implemented and new design released. This is all documented as an ECO.
When we need to fix a vlsi design, we basically insert/delete gates or change wires. This alters the mask for metal layers or base layers. ECO is the process of minimizing those changes in mask, so that we don't make too many changes to mask set. If we have to make too many changes, then there's no benefit of doing an ECO. In such cases, we should start design from step 1 instead of marking changes as ECO.
The initial design for any project is named as 1p0 or A0 design. We release the mask set for this to fab, and get the fabricated chip. If the chip comes back with bugs, we try to find out if those bugs can be fixed by just changing metal masks (instead of changing base layer mask too). If we can fix bugs by just changing metal masks, it's less costly both in terms of time and money. This new design with only metal mask changes is usually called as 1p1, 1p2 or A1, A2 etc. However, if the changes are more complex, we may need to make changes to base layer masks too. This new design with base layer mask changes are usually called 2p0, 2p1 or B0, C0, etc. Thus A, B, C refers to major design changes involving base mask, while B1, B2, B3 etc refer to minor design changes involving metal mask only.
If the change can be done by changing metal layers only, then it's called "metal eco", while if it involves base mask changes, then it's called "all layer eco". so, "metal eco" are minor revisions as B1, B2, etc, while "all layer eco" are major revision as A0, B0, C0, etc.
ECO type: pre-mask vs post-mask: ECO can be of 2 types based on when the change is made in design:
1. pre-mask => premask is when mask isn't ready yet, i.e for making very small changes while the design is still not taped out. Here, no masks have been ordered. So we can make any change we want. However, we do not want to run the entire design from step 1, since we may have fixed a lot of issues manually in the design, and ripping the whole design to fix some minor issues is prohibitive in terms of cost and time. So, we put the design in pre-mask eco mode, which says that the changes will be localized to affected areas only, so do not disrupt the whole design. Keep changes as small as possible. Here we can change both metal layer as well as base layer. So we are allowed to make complex design changes here, as we have the flexibility to change any gate or wire. We use the term pre-mask to mean that base layer changes are allowed in design. So, an "all layer eco" is basically called pre-mask eco, even though mask may have already been released.
2. postmask => postmask is for making changes after the mask has been released. We find out late that their is a bug in design. In such cases, we make metal mask and/or base layer mask changes. We need base layer mask changes when the changes are extensive and more complex. These get classified as pre-mask eco, even though they are post-mask. However, if the changes are small and can be implemented by changing metal layers only, we call it "metal eco". This is what is usually referred to as "post mask". For postmask eco, spare cells are used (as it's metal only), while for premask, new cells are added or existing cells modified.
ECO type: Functional vs Non-Functional: ECO can be of 2 types based on what kind of change is involved:
1. Functional ECO: change the functionality of the design. i.e when an and gate is added to some logic path, that is a Functional ECO.
2. Non-Functional ECO: does NOT change the functionality of the design, but deal with timing, design rule or signal integrity. i.e when a wire is moved to make extra spacing, it's a Non-Functional ECO.
Both Synopsys and Cadence tools support ECO flow, so that changes can be easily made from within the tools.
For Cadence, Conformal tool is usually used for making ECO, while for Synopsys, Design Compiler (DC) tool is used.