VLSI Introduction

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Last Updated: Wednesday, 08 November 2023 00:30

Published: Wednesday, 20 January 2021 19:00

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VLSI Introduction:

VLSI: Very Large Scale Integration. This is the field of Electrical/Electronic Engineering that deals with the science of designing circuits and building them on chips.

There are many preliminary courses that you will need to take, before you can start designing chips.

Circuits are built using passive components: R, L, C.

On top of above 3, we have an active component known as "transistor" that brought about all the revolution in electronics. Transistor is basically an "electronic switch" that you can turn ON or OFF using voltage signal (by contrast, a manual switch at home requires physical force to turn it on or off). When we talk about VLSI or solid state, we are almost exclusively talking about transistors. Transistors are what made all modern chips possible, so it's one of the greatest invention that gave us all modern electronics today.

VLSI History:

Since 1950's, all these passive elements used to be stand alone devices. They were big, and to make any circuit out of them required considerable space. Then came active element, transistors. Transistors used to be stand alone devices too, similar to Resistors and capacitors. However, researchers started looking into ways of making these transistors smaller and getting a lot of them to be etched out on a single base. Silicon became a compound of choice. This gave birth to LSI in 1950's.  With advent of LSI, we started building transistors on Silicon wafers and integrating a lot of them on the same silicon wafer. This greatly reduced the size of each transistors and allowed thousands of transistors to be put together close to each other connected by miniature wires which were themselves etched on silicon. The number of transistors being etched on a single wafer kept on increasing which gave birth to VLSI. A very good history of VLSI and how small the dimensions of these transistor were in each technology can be found on this link:

https://en.wikichip.org/wiki/technology_node

FEOL vs BEOL:

FEOL (Front End of Line) refers to steps associated with transistor fabrication. Transistor fabrication on silicon involves 10-50 steps for modern CMOS tech. It needs the most advanced and cutting edge tools and tech to build the smallest transistors. It takes 30 days or more to complete all fab steps associated with a transistor and get it out. Photomasks for transistors are also the most expensive ones, as they need to have very high accuracy for the small size of the transistors.

BEOL (Back End of Line) refers to steps associated after the transistors layers are done. This is where interconnects to transistors are built using metal layers. Fabricating these metal layers isn't as complex as fabricating the transistors. Once transistor layers are deposited properly and transistors are functioning, building metal layers on top of it goes faster. It's 2 masks for each metal layer (one for horizontal connection and other for vertical cuts to connect one layer to another). These masks are cheaper as the width of metal layers isn't as small as transistor gate length. Each metal layer takes a day to go thru the fab, so 10 metal layers will take about 10 days. As FEOL dimensions shrink, BEOL dimensions also need to shrink, so that the overall gain in density can be achieved.

Full node (FN) vs Half node (HN):

Transistors size can get reduced by any amount from one node to other. However, it would be very expensive to introduce a new node just for little bit of size reduction. Reason is that size reduction of transistors usually imply that associated tools used in Fab have to be changed to design with lower transistor size, which is very costly. A rule that has been followed in Semiconductor fabrication is that a transistor reduction that would give 2X the transistors density is worth the cost. The lower size of chip due to 2X the density implies chip cost has been cut into half, which is able to absorb the extra cost of fab retooling. To get to 2X density, both X and Y dimension of chip has to decrease by 0.7X (since 0.7X * 0.7y = 0.5xy => half the size of original chip). So, we not only reduce the length of transistor by 0.7X, but we also decrease the width of transistor by 0.7X. This is known as a full node.So going from 1um node to 0.um node is a full node transition which is very costly. Full node transistion has been happening every 2 years, implying transistor density is doubling every 2 years. This is also known as Gordon Moore's Law, who famously predicted this in 1965. However, companied don't want to sit idle for 2 full years, without showing any improvement. To address this, these chip companies introduced a half node. Half node is a 10% reduction in size of transistors in fab without changing the tools completely. Design was done in such a way that existing design could be used, and reduction in size was done entirely in fab. This gave some incremental improvement without redesigning the circuit or re-tooling the fab. This came to be known as half node and came in between 2 full nodes. So, a half node would give 20% (since 0.9X * 0.9y = 0.8xy) reduction in IC size, while full node would give 50% reduction in size.

Every 4 years, we would get transistor length reduction to be 1/2 of it's current one (since every 2 years, it goes down by 0.7X, so every 4 years it's 0.7*0.7=0.49 or almost half). That is why FN tech goes like this 1um -> 500nm ->  250nm -> 130nm -> 65nm -> 32nm -> 16nm -> 7nm -> 3nm, and so on.

Tech Node:

A technology node of certian um or nm usually refers to the smallest dimension that can be etched out on the silicon. Usually it's the gate length of the transistor that has the smallest dimension. Also, the gate length of a transistor has inverse relationship to the performance, as shorter transistor length implies a higher current, and hence faster speed. Since the transistors were invented, tech nodes referred to transistor length (so a 2um node meant that the transistors on this node have 2um gate length with slight variations. You can't etch out a gate with length < 2um on this node). Along with this we also got a 2X increase in density with every full node. But as we got to smaller transistor lengths, it was observed that just reducing transistor gate length didn't guarantee a 2X increase in density. It was limited by how much closer you could place transistors to each other. If you couldn't scale that distance to half every 2 years, you wouldn't get to 2X scaling. So, 2X density improvement became the new definition for defining a full node. The nm or um number for tech node that used to refer to gate length didn't necessarily refer to gate length anymore, though it's close. Some people starting calling the half pitch as the better  definition for a tech node. Pitch is defined as the distance between 2 adjacent gates. Min pitch refers to the closest you can get 2 gates to each other while still having space to make contacts to both the gates and the active source/drain regions. Half pitch is half of this distance, and turns out that half pitch is a very relevant number when talking about density improvement. So, a lot of later tech nodes since 2000 use their tech node "nm" to refer to the "half pitch" or "gate length" or to something smaller than both of these. That "nm" number is more of a marketing ploy now. So, keep that in mind when going thru the tech nodes below.

Tech node timeframe is as below. I'm showing full node process only.

• 50um - 10um => 50um was the first process developed in mid 1960's for building transistors on wafers. The typical wafer size (diameter) was < 1 inch (only 22mm). 50um is the typical thickness of human hair (100um is 1/10th of a mm), so transistors of this size could possibly be seen by naked human eyes (though microscope will be necessary as these 50um lines will be very close to each other and hence difficult to distinguish). Going from 50um to 10um, wafer size increased to 2 inch. 10um was being developed actively during early 1970's. Intel' 8008 was developed on 10um tech.
• 10um - 1um => From mid 1970's to late 1980's, transistor size kept on decreasing, while wafer size kept on increasing (from 1 inch all the way to 6 inch or 150mm), resulting in even greater transistors per wafer. Bulk CMOS tech was being used with voltages at 5V. Only one metal layer was being used for interconnect, though 2 metal layers started getting used for 2um or below.. Intel's 8086 series was being developed during this time using 1 tech nodes close to 1um.
• 1 um => introduced in late 1980's. Intel's 80386 and 80486 were based off this. 1um tech was big step, as transistors of this size were considered infeasible just a decade or two back.
• 700 nm => Introduced in early 1990's, it was a full node followup to 1um tech. 3 metal layers were being used here. Intel's Pentium Pro was built on this process node.
• 500 nm => Commercial ICs started getting produced using 0.5um tech in 1993. It was called a half micron process. 4 metal layers of Al-Cu (Aluminum Copper) started getting used. Oxide thickness was reduced to about 10nm. The process typically had a Threshold voltage of 0.5V and a supply voltage of 3.3 V.
• 350 nm => Commercial production using 350nm started in late 1995. Number of metal layers went to 5 with oxide thickness further reduced to 6nm. Intel's Pentium and Pentium II were built on this.
• 250 nm => Also known as "quarter micron" process,  Intel along with other leading semiC companies entered 0.25um process in 1997. Intel's process used 200 mm wafers, SiO2 dielectric and polysilicon electrodes. It used Aluminum inter-connects. Intel also made a smaller chip using 5% shrink to original design rules which used. Gate pitch and interconnect pitch was about 500nm-700nm. 
• 180 nm => This was introduced in 1999 by Intel, TI, IBM and TSMC. Number of metal layers went to 7. Gate pitch and interconnect pitch was about 450nm-500nm. 
• 130 nm => This was introduced in 2001 by Intel, TI, IBM and TSMC. Number of metal layers went to 8. Gate pitch and interconnect pitch was about 350nm. SOI process instead of Bulk started getting used at AMD, IBM, etc which was basically silicon on insulator which allowed the body to float instead of being tied to power supply as in bulk tech.
• 90 nm => This was introduced in 2003. Gate pitch and interconnect pitch was about 250nm. At 90nm, 300 mm (12 inch) wafers started getting used, which was a big step from 200mm or 8 inch wafers that were being used before than.
• 65 nm => This was introduced in 2006. Gate pitch and interconnect pitch was about 200nm. 
• 45 nm => Commercial manufacturing using 45 nm process began in 2007. Intel's 45 nm process was the first time high-k + metal gate transistors was used in high-volume manufacturing process. Before this, poly was being used for gate, which had very high resistivity. Gate pitch and interconnect pitch was about 160nm-180nm. 
• 32nm => 32nm manufacturing began in 2010. Metal layers went to 9 to 11 layers. 193nm Immersion Lithography was being used for 32nm. Gate length was 30nm, even though node was 32nm. Gate pitch and interconnect pitch was about 100nm-130nm. Supply voltages came down to 1V or below for the first time. 28nm was a half node introduced a year later, and was a stop gap b/w 32nm and 22nm.
• 22 nm => 22nm manufacturing for processors began in 2012, although memories were being built on this node since 2008. Until 22nm, we were using planar transistors that were conventional transistors that had been used since CMOS tech came into existence. However, it was becoming more difficult to scale planar transistors as sizes kept on shrinking. Companies were looking for alternatives. Fin based 3D transistors were actively being researched and showed promise. The 22 nm became Intel's first generation of Tri-gate FinFET transistors and the first such transistor on the market. Other companies didn't jump to FinFET bandwagon yet and continued with planar transistors. Intel's core i3, i5 and i7 were built on this new tech. Gate pitch and interconnect pitch was about 80nm-100nm. Supply voltages came further down to 0.7V-0.8V.  20nm was a half node introduced in 2014 followed by a 16nm Full Node in late 2015. 20nm was still in Planar technology while 16nm moved to FinFet.
• 16nm / 14nm => 16nm was the first time industry moved away completely from Planar transistor to FinFet transistors. Things got more confusing as "nm" no longer referred to gate length, and different companies started adopting different naming convention as per their choice. There is also confusion as to whether 16nm or 14 nm is a full node. Based on Maths, looks like 15nm should be full node. Some companies went with 16nm as their full node, while others went with 14nm. Manufacturing using 16nm/14nm began in 2014/2015. Both 14nm and 16nm were still based on 193nm Immersion Lithography. Supply voltages were same around 0.7V.
  
  • 16nm: TSMC introduced their first 16nm FinFet process known as 16FF, followed by later revisions as shown below. Gate length was 34 nm (not 16nm), with Fin pitch at 48nm and Gate pitch at 90nm.
    
    • 16FF => 16nm FinFet process. It used the same 20nm BEOL.
    • 16FF+ => Improved 16nm FF process to give 10-15% perf improvement
    • 16FFC => 16nm FinFet Compact was the refined version of earlier process which reduced cost by using less masks, and used half the power.
  • 14nm: Intel introduced their 14nm process as P1272/P1273. Samsung introduced 14LPE (Low Power Early), 14LPP (Low Power Performance), 14LPC and 14LPU. IBM (Fabs were sold to Global Foundary in 2014) 14HP process started manufacturing a bit later in 2017. UMC also started mass manufacturing of their 14nm process in 2017.  All these had smaller gate length varying from 20nm-30nm (nowhere close to 14nm). Fin pitch was 42nm, while gate pitch was at 70nm-80nm. Minimum metal pitch was 50nm-60nm. Fin width was 8nm, with Fin height at 40nm. Intel 14nm process had further refinements with 14nm+, 14nm++ which yielded up to 50% less power and 30%-40% higher drive current. Intel's 14nm process was the densest, with 1.5X raw logic density when compared to other leading Fabs.
• 14 nm =>
• 10nm
• 7nm
• 5nm
• 3nm
• 2nm

Diff node Scaling:

VLSI Topics:

This is the sequence of topics we'll cover in VLSI section:

1. R, L, C: A lot of simple circuits may be made using R,L and C. These are simple to understand.

2. Solid state devices: Transistors, diodes. These are more difficult to understand.

3. Digital Library cells:

4. Digital Hardware language:

5. CAD tools

6. Analog design

7.

Links:

1. Sunburst: One of the best places to learn digital vlsi design: http://www.sunburst-design.com/

Here they offer a lot of paid training. You don't need to take any paid courses. They do have a lot of free papers, that have a lot of useful info. http://www.sunburst-design.com/papers/

I'll list these papers in different section as we talk about the various topics.

2. Teamvlsi: I saw a few good topics covered here. They also have a youtube channel with good videos. Link: https://teamvlsi.com

3.