vlsi cad design flow

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Published: Friday, 12 October 2018 04:34

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VLSI cad design flow and associated tools:

Vlsi design flow involves making transistors in a particular technology by a Fab company. These Fab companies then give their transistor models, as well as pre designed digital as well as analog logic to bee used by the tools provided by 3rd party companies. These CAD design tools are run for different stages of design. We'll look at design flows using both proprietery tools and open source tools. For proprietery tools, we'll look at tools from Cadence and Synopsys. For open source, we'll look at Qflow.

Proprietary and Open Source CAD Design Tools

There are 2 big players in VLSI CAD design tools: Synopsys and Cadence. Both of them are public companies with revenues in order of $5B/year. Other smaller players are Mentor Graphics, Ansys, etc. All big players keep buying smaller players, who in turn buy even smaller players. Ultimately, there will be just 2 EDA companies which will serve most of the EDA market: Cadence and Synopsys.

Synopsys: Synopsys was founded in 1986. It was initially established as "Optimal Solutions". It acquired "Magma Design Automation" for about $0.5B in 2011, which along with Mentor Graphics were the 3rd and 4th biggest players in EDA market at that time. Synopsys had revenue of $5B and profits of $1B as of 2020. Synopsys releases versions of their tools almost once every quarter. On top of that, if some bugs were found and fixed in the previous release, they release service pack (SP) for that. So, for ex if they provide version of a tool as 2010.06-SP4 => it's released in year=2010, month=6, and is service pack 4.

Cadence: Cadence Inc was founded in 1988 by the merger of SDA Systems and ECAD inc. It has $3B in revenue and $1B in profits as of 2020.

Mentor Graphics (MG): MG was founded in 1981, and went public in 1984. Cadence was about to purchase "Mentor Graphics" in 2007, but then withdrew the offer. MG was finally purchased by Siemens in 2017, and renamed "Siemens EDA".

Magma Design Automation: MAGMA was founded in 1997, and rounded up the top 4 players in the EDA market. It initially focused on physical design software, but later broadened it's product protfolio to complete with other 3 top players. Magma's peak revenue was $200M in 2008. It was sold to Synopsys in 2011.

Ansys: Ansys was founded in 1970. It has revenues of $2B and profits of $0.5B as of 2020. However, it's VLSI CAD tool portfolio is pretty small, as most of it's products are in "finite element analysis" which is used to simulate computer models of structures, electronics, or machine components for analyzing the strength, toughness, etc.

Open Source: Next comes Open Source tools. These are fragmented, and no organization has taken the burden of developing them (No equivalent of Open Source Software or Linux here). These are primarily developed by individuals here and there.

These are the VLSI CAD software developed by various companies. We'll learn in detail about these tools in their respective sections. This is just an introductory material.

Digital ckt library considerations:

Before we can use CAD tools for digital design, we need to have digital libraries. Digital ckt library has all gates as AND, OR, FLOP, LATCH, etc that are needed to design digital circuit. if the chip is purely digital, then we just go with lowest nm Technology, as it gives the lowest area and hence lowest cost (since cost of a chip is directly proportional to area). However, when we have mixed signal design, where a significant portion of design is analog and only a small portion is digital (maybe 80-90% is analog and 10-20% is digital), then the choice of tech node is not that easy. We want to go with appropriate Tech node depending on our size and speed requirement. Usually in mixed signal chips, analog is bigger portion, so going with very low nm doesn't give much area saving to the total chip (since only digital shrinks, while analog is almost same size). Also, analog needs transistors which can withstand higher voltages, so gates with thicker oxide and larger L needed (large L implies lower current, so lower speed, but can withstand higher Vds voltage).

For a typical (typ) voltage of "V" volts, we guarantee proper operation of circuit at 90% of V and 110% of V. We allow these +/- 10% voltage variation to account for IR drop, voltage overshoot etc. These become max and min voltages for our chip operation. Besides these max, min and typ voltages, we also have vbox voltages.

vbox: (run at normal temp). These are test conditions to bound the part. These are extremely high or low voltages to which the part is never going to get exposed, but may be useful to run nonetheless, as they may point to fragile parts which are on cusp of failing. IDDQ Scan pattern is run at vbox hi/lo to make sure scan works. There is also "vburn in" cond, to detect early failure, done at high voltages. vbox/vburnin done for only digital ckt, so there has to be way to disable analog ckt, while doing vbox tests. scan_iddq tests run before and after vbox and any appreciable change in iddq is taken as a sign of failure.  

1. vbox_hi : assume high voltage extremes can be used to accelerate failure mechanisms due to infant mortality failures. Vbox_hi puts lowest voltage that causes gate oxide to break or Bvdii (drn to src breakdown or drn/src to body jn breakdown) to occur. For Tox=75A, gate oxide breaks at 1000V/um*.0075um=7.5V, Bvdii is much lower at 2.5V, then Vbox_hi=2.5V for 1.5V transistor in a given 180nm tech.
2. vbox_lo : assume Low voltage extremes detect failure mechanisms that would have occurred later in the product's life. Vbox_lo takes max threshold voltage of Nmos or Pmos and scales it upward by 40%. So, for 180nm tech, 1.5V transistor, Vth=0.7V, so Vbox_lo=0.7*1.4=0.98V. But sometimes ckt can't even get out of PORZ 9power on reset Z) at such low voltages, so design should be modified to allow operation of digital to happen at such low voltage.

400nm (0.4um) Tech Lib: This large nm tech is used in many mixed signal IC design. Digital transistors can handle upto 4V.

400nm tech is 3.3V digital library. Lmin=0.4um drawn (no shrink, so Final L=0.4um).
gate density = 14K gates/mm^2 for 2LM (2 layer metal), 19K gates/mm^2 for 3LM (3 layer metal), 23K gates/mm^2 for 4LM (3 layer metal)
nom: N_25C_3.3V (room temp, nominal voltage with nominal process)
max: W_150C_3.0V (max op temp of 150C, 10% below nom voltage) = max delay
min: S_-40C_3.6V (min op temp of -40C, 10% above nom voltage) = min delay

vbox:
hi: S_27C_5.00V (at max voltage part can run at)
lo: W_27C_1.02V (at min voltage part can run at)

210nm (0.21um) Tech lib: Even though digital ckt operates at 1.8V, transistors can survive upto 3.6V.

210nm tech is 1.8V digital library. Lmin=0.6um drawn (shrink=0.35, so Final L=0.21um)
gate density = 50K gates/mm^2 for 3LM, 75K gates/mm^2 for 4LM, 80K gates/mm^2 for 5LM. Gate density has improved substantially here, so it's advantageous to move to this 210nm tech, provided analog transistors can operate at such low voltage.
nom: N_25C_1.80V (room temp, nominal voltage with nominal process)
max: W_150C_1.65V (max op temp of 150C, 10% below nom voltage) = max delay
min: S_-40C_1.95V (min op temp of -40C, 10% above nom voltage) = min delay

vbox:
hi: S_25C_3.20V (at max voltage part can run at) => helpful to find hold margin,
lo: W_25C_0.95V (at min voltage part can run at) => usually not relevant as digital circuit can't run at such low voltage. Nevertheless we still run Timing runs to make sure all timing runs are clean.

Libraries with RC variants:

So far, we considered only the transistor in the process part of PVT. But inreality Resistance, capacitance and transistor all have process dependency.

VLSI Digital Flow:

Below are the various steps in taking an RTL to final gds to be taped out.

1. Synthesis: (DFT test synthesis is done within the synthesis tool). RTL to  gate synthesis done here.

The tool here takes the RTL provided and generates a gate level netlist for it. This gate level netlist doesn't have any floorplan or pin locations. It's just a verilog file containing the connections of all the gates. We take it Place and Route tool, which does the actual placement.

2. PnR: The synthesized netlist obtained in step 1 above is placed and routed

max/min delay libs. (W_150_1.65_CORE/CTS.db and S_-40_1.95_CORE/CTS.db used)
Leffile used: tech.lef and core.lef (pml30_lbc8_tech_3layer.lef & pml30_lbc8_core_2pin.lef used)
min/max cap tables used for metals (3m_nom/max/minC_nom/max/minvia.capTbl)
sdc file: we point to sdc file from DC synthesis which has all constraints (as i/o delay, clk waveform/freq, false_paths, etc)

A. create floorplan. provide floorplan size, add power routes and IO pins.

B. create max/min views for func/scan:
func_max = worst case lib, worst case capTbl, and constraints.sdc file from DC synthesis.
func_min =  best case lib,  best case capTbl, and constraints.sdc file from DC synthesis.
scan_max = worst case lib, worst case capTbl, and scan.sdc file.
scan_min =  best case lib,  best case capTbl, and scan.sdc file.

- constraints.sdc file has all clks/generated clks defined and sets case analysis with scan_mode=0.
- scan.sdc file has scan clk defined and sets case analysis with scan_mode=1. Here, no other clks need to be defined as in scan mode, scan_clk should be feeding to all the flops.

C. place:
- set analysis view for setup to func_max and for hold to func_min.
- propagate clk and run pre-place setup timing.
- place IO buffers, place design and then rerun setup timing.
- place spares, and then do post optimization to fix setup and drv (if required), and then rerun setup timing

D. CTS:
- we set case analysis with scan_mode=1. This is so that CTS is done using single scan clk. That way all clks are balanced in scan mode.
- CTS done honoring clks and skews,etc in .ctstch file for each clk specified (main clk, spi clk). generated clks not specified since we do CTS thru generated clks. Note: if we have scan, then we use scan_clk port for CTS (which is usually spi_clk) and no other clks are needed.
- we set case analysis back to scan_mode=0. Then run setup and hold. Many hold failures will be seen as clk skew will cause extra delay. It will cause seup issues also, if our setup slack was very small to begin with. However, some setup/hold paths may get fixed too.
- do post cts opt to fix setup, drv. Hold is usually not fixed here, as we'll fix it during route with some slack margin. Then run setup and hold.

E. Route:
- route done, and then native extractor (RC extract with effortlevel low) used for the first time to extract parasitics.
- setup and hold run.
- Opt done (with hold slack to 0.2ns, setup slack to 0.05ns) to fix setup, hold and drv.

F. STA:
- native extractor (RC extract with effortlevel low) rerun. Native extractor uses cap tables to look up Res, Cap, so is less accurate than QRC extractor.
- set analysis view for setup to func_max, func_min, scan_max, scan_min,  and for hold to func_max, func_min, scan_max, scan_min. For the first time, we run setup/hold for all views. Usually we see setup/hold time failures (as setup is run in func_min and hold in func_max for the first time here) here as well as scan timing failures (as scan mode is run for the first time for setup/hold) here. For our designs, we mostly see hold time failures, as setup has good slack to start with.
- Run setup and hold, and do post sta opt (if needed) to fix hold and drv.

G. Signoff:
- QRC extractor (RC extract with effortlevel signoff, coupled set to true) run. QRC extractor solves maxwell's 3D eqn to arrive at res, cap and does NOT use cap tables, so is more accurate.
- Run setup and hold, and do post sta opt (if needed) to fix hold (hold slack of 0.1ns), setup (hold slack of 0ns) and drv.

H. Filler: Filler cells added

I. Final checks: final connectivity, geometry and antenna checks done.

J. Export final: Put min/max SPEF, DEF and Verilog netlist in FinalFiles dir.
- max/min SPEF files generated using QRC extractor (RC extract with effortlevel signoff, coupled set to true).
- DEF and verilog netlist written out.

3. Timing: Now timing is run using some signoff timing tool that guarantees that all valid paths are timed and shows any failing paths.

- PT should see exactly the same paths that VDIO ETS was seeing.
- both setup/hold run for scan/noscan at min/max delay (wc/bc PVT) corners. Total of 8 separate runs.
- additional vbox hi/lo corner run for scan mode
- min/max SDF file generated

 - flow (PT):
  - Running PT for noscan_min, noscan_max, scan_min, scan_max, scan_vbox_min(vbox_hi), scan_vbox_max(vbox_lo) => repeat 6 times
   - set lib to std cell lib min/max lib (for vbox choose appr PVT)
   - read gate level verilog
   - read min/max spef file
   - read sdc constraint file (func or scan, for vbox choose scan constraint)
   - set analysis type to single mode (run only one corner at a time - max_func, min_func, max_scan, min_scan, max_vbox, min_vbox)
   - do checks, report timing for both setup/hold
  - Running PT for max and min sdf generation => repeat 2 times for max and min
   - set lib to std cell lib min/max lib
   - read gate level verilog
   - read min/max spef file
   - do checks, write sdf for min/max corners.

 - flow (ETS):
  - Running ETS for noscan_min, noscan_max, scan_min, scan_max, scan_vbox_min(vbox_hi), scan_vbox_max(vbox_lo) => repeat 2 times (one for vbox)
   - read lib for std cell lib min/max lib
   - read gate level verilog
   - create views  (same as in EDI)
     - create wc/bc std cell lib corner = wc_lib_set, bc_lib_set
     - create wc/bc rc corner = max_rc, min_rc (specify cap_table as well as qx_tech_file, but ETS only supports QRC extractor (notcap table based). However we soecify spef below so that gets used)
     - create constranits by specifying sdc files for func and scan mode.
     - create 4 analysis views => func_max, func_min, scan_max, scan_min
   - set analysis view => -setup {func_max func_min scan_max scan_min} -hold {func_max func_min  scan_max scan_min}
   - read min/max spef file => rc corner needs to be specified here, but isn't used for anything (just a syntax thing). spef files can be read only after analysis view is set.
   - set analysis type to bcwc mode (uses max delay for all paths during setup checks and min delay for all paths during hold check from min/max lib)
   - write sdf for min/max corners for view func_max, func_min (views don't matter for sdf files)
   - do checks, report timing for both setup/hold for view func_max, func_min, scan_max and scan_min separately in 8 diff reports.
   

4. Formal verification: Now we need to verify that the netlist generated by synthesis tool and PnR tool is exactly the same as RTL. This is called Formal Verification, which is the process of running all possible patterns on both RTL and gate netlist.

Formal Verification is supposed to be a push button thing, as Synthesized netlist is generated by the tool vendor, and it verifies the synthesized netlist with RTL to make sure it's correct. It should pass by default, else synthesis tool or LEC tool has a bug. However, various lib models may cause inconsistency.

Cadence Conformal is considered gold standard in LEC as it allows any 3rd party netlist to be checked against RTL. Synopsys's Formality requires some hints from synthesis tool to help it. Jasper is the latest Verification tool from Cadence that can do lot more than just formal verification. Jasper provides a wide range of Applications (Apps) covering: Formal Property Verification, Sequential Equivalence Checking, Low-Power Verification, Connectivity Verification, Config/Status Register Verification, X-Propagation Analysis, Structural Property Synthesis, and Behavioral Property Synthesis (just to name a few).

5. Scan Patterns DFT Tool: Once we have done scan stitching and added all scan related logic, it's time to run Scan patterns, and check what kind of coverage they provide.

Just running scan patterns doesn't guarantee that the patterns will run corrctly on the design. So, we also run scan simulations - which is essentially running scan patterns on gate level netlist (with sdf annotation) by writing a special testcase. Above 2 tools already provide built in testcase that we can use to run sims on patterns. This is called scan simulation.

6. RTL sims: Here we write bunch of testcases and run it on RTL. If the RTL logic has multiple power domains, then Power aware RTL (PARTL) sims can also be run.

7. Gate sims: Here we run sims on final gate netlist 9from PnR tool) instead of on RTL.

8. spyglass (optional)
9. icfb (to upload digital design to top level design)
10. patgen
11. power: power rail analysis using Encounter Power system (EPS from Cadence),
           redhawk (??) => for EMIR (used in veridian), Totem
           NEW: VOLTUS: power analysis tool (cadence). IC chip power consumption, IR drop, and electromigration (EM).