open source hardware design tools - introduction

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Last Updated: Thursday, 19 October 2023 21:47
Published: Thursday, 28 December 2017 12:37
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This section deals with all aspects of hardware design.

Open source tools:

There has been a lot of development in open source CAD tools for VLSI design. Though these are not state of the art, but they are good enough to fabricate multi million gate designs in 14nm and above. A lot of developments have taken place, and as of 2023, tons of chips have been fabricated relying entirely on open source tools. FOSSi (Free and Open Source Silicon) Foundation ( https://fossi-foundation.org ) is behind this development too.

Check this link on youtube for latest developments: https://www.youtube.com/watch?v=OmEbzRp_NGg

In keeping up with philosophy of open source, I'm going to list most relevant open source tools that can be used to design hardware. In the past, you had to assemble all these open source tools, and then use them together to start from RTL and get to the final gds. However, now as of 2023, there are multiple flows available, that take these separate open source tools, put them in a package, and just download the flow kit. This has made things lot easier.

For anyone to be able to fabricate the final chip, we need 3 components:

  • PDK (Process Design Kit) from fab: There are tons of fabs in US and abroad that take your design in GDS format, and print it in silicon. TSMC is most well known which is a pure-play silicon foundary. Samsung, Intel, etc have their own Foundary for chips that they design in house.
    • SKywater Tech (https://www.skywatertechnology.com): Skywater Tech is the only US based pure-play silicon Foundary, based in Bloomington, Minnesota. It was formed in 2017 and went public in 2021. It has collaborated with Efabless and Google to create the first open source chip manufacturing program. They fabricate chips in 90nm and 130nm CMOS process. They have open sourced Sky 130nm (S130) PDK, which is available on github. Link: https://github.com/google/skywater-pdk. This was the last hurdle for open source tool chain to clear, as prior to this, there were no real world open source PDK. There were some experimental PDK, but not ones that could take your design and fabricate silicon.
    • Efabless (https://efabless.com): Efabless is another Fab Company which is a crowdsourcing design platform for custom silicon. They have Multi Project wafer (MPW) shuttles that anyone can get their silicon design on. They use
  • Use tool chain flow from RTL to GDS
  • Flow for submitting the GDS to fab
  • Librarystart from RTL to

These are the 2 flowchain (or tool chain) that I'm going to talk about.

 

 

Open Road:

This is the latest open source toolflow chain that has industry heavyweights behind it. It was launched in 2018 with DARPA. UC San Diego is leading the effort with involvement from companies as Qualcomm, ARM, etc.

Official website: https://theopenroadproject.org/

Resource link on above site talks about all the steps needed => https://theopenroadproject.org/resources/

All User uides on installation/setup/running are here (all relevant docs are here): https://openroad.readthedocs.io/en/latest/

Start from here which starts with flow-scripts: https://openroad-flow-scripts.readthedocs.io/en/latest/

Ubuntu and CentOS are both supported. I'll go with Ubuntu, since CentOS isn't supported officially anymore (as of 2023). So lot of stuff in CentOS breaks with installation on newer laptops (due to older drivers not working any more). We'll go with local installation of open road on our Linux system.

Steps here: https://openroad-flow-scripts.readthedocs.io/en/latest/user/BuildLocally.html

 

 

 

 

 

Qflow:

This was a flow that was developed around 2018. The website is http://opencircuitdesign.com.  It has links to all open source tools that can actually be used to design and simulate real circuit. The founder of this website, Tim Edwards, has actually designed and fabricated a microcontroller using only the open source tools (in 2018), and it was a first time silicon success (i.e no bugs in fabricated chip). Some of the open source tools have been written by him, while some he got from others. But he combined all of them, put them in a neat flow, that can take an RTL, and generate gds. No doubt, he has done an amazing job. I've followed his instructions step and step, and have been able to get the whole toolflow working on Linux OS "CentOS Linux release 7.5.1804". Below, I'm going to show step by step instructions on how to get started with his toolflow, called "qflow".

 Before we go into the toolflow, we need design of transistors, gates etc that can be fabricated in fabs. OSU (Oklahoma State universiyty) provides all of this at this link: https://vlsiarch.ecen.okstate.edu/flow/. These are included as part of tool flow "qflow", so you do not need to download anything from here, but it's good to keep a copy of the material in a separate directory on your machine.

The download link at bottom of this (http://vlsiarch.ecen.okstate.edu/flows) page provides all design related files needed for different cad tool flows (synopsys and cadence and mosis). Using these cad tool flow, full designs can be done and chips fabricated in different fabs (AMI =American Microsystems Inc (purchased by OnSemi) and TSMC). These open design related files were developed by this prof, James Stine. He was initially working at IIT (Illinois Insttitute of Tech), and then moved o to OSU (Oklahoma State University). So, you will find material from both places, but OSU stuff is latest, so use that for design flow.

If you follow the link, you will see 3 dir: These dir have tech files related to these nodes => AMI 0.5um, AMI 0.35um, TSMC 0.25um, TSMC 0.18um, FreePDK 45nm. FreePDK 45nm has been designed jointly with North Carolina State University, and is the most advanced node currently supported. The 3 dir you see are:

1. FreePDK_SRC => It has 45nm design files. In this there is *.tar.gz. Download that file and extract it in a dir named "FreePDK_SRC" (or any other name, doesn't matter). It will create a dir named "OSU_FreePDK". Inside it are 2 *.tar.gz. Extract both of them to create 2 new dir: OSU_FreePDK_Tech and osu_freepdk_1.0. We will not bother with 45nm design at all, as it's very advanced for our experimental purpose.

2. MOSIS_SCMOS => This has MOSIS (Metal Oxide Semiconductor Implementation Service) SCMOS (scalable CMOS) design files. MOSIS is a middle man foundary service that provides fab access to TSMC, GF (global Foundaries), AMS and AMI (now part of OnSemi). It has IIT and OSU stdcell libraries. We will not bother with IIT libs, as they are older.We will only deal with these 2 dir (download these 2 tar.gz files in a dir named "MOSIS_SCMOS" (or any other name, doesn't matter):

A. osu_soc_v2.7 => Inside this is a tar.gz file. Download and extract it in a dir named "osu_soc_v2.7" ((or any other name, doesn't matter). It will create 2 subdir "cadence" and "synopsys", as shown in the link. This is the version that is used by "qflow".

B. osu_stdcells_v2.4 => Inside this there are 3 tar.gz files. Download and extract it in a dir named "osu_stdcells_v2.4" ((or any other name, doesn't matter). After extracting all 3 of them, it will create 3 subdir "flow", "lib" and "ref_designs", as shown in the link.

3. stdcell_datasheet => This has datasheet for all stdcells in different tech (AMI 0.6um, AMI 0.5um, AMI 0.35um, TSMC 0.25um, TSMC 0.18um, FreePDK 45nm). We do not need to download anything from this dir, as it is for informative purpose only. We will need to refer to this datasheet from time to time though, so will be nice to keep this link bookmarked.

In my case, after downloading and extracting everything, dir structure looks like this:

/home/vlsi/osu_flows

  • FreePDK_SRC => It has files for FreePDK 45nm
    • OSU_FreePDK
      •  OSU_FreePDK_Tech
        • cdssetup
        • lib
        • techfile
      • osu_freepdk_1.0
        • flow
        • lib
        • ref_design
  • MOSIS_SCMOS => It has files for AMI 0.5um, AMI 0.35um, TSMC 0.25um, TSMC 0.18um
    • osu_stdcells_v2.4
      • flow
      • lib
      • ref_design
    • osu_soc_v2.7
      • cadence
        • flow
        • lib
        • ref_design
      • synopsys
        • flow
        • lib
        • ref_design
  • flow => flow dir has techfiles, tcl scripts
  • lib => lib dir has .v files, .lef files
  • ref_design => ref_design dir has a reference design of a mips processor, that can be used as a sample design to work with.

First, we need to understand chip (IC) design, and then use this understanding for system design, so that we can have a hardware that can actually do something. Chip design will be explained in a separate section. Here I'll go with the toolflow "qlow" instructions and setup. You will need to know the design process, before you go into this toolflow section.