vesta - static timing analysis tool

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Last Updated: Thursday, 06 June 2019 01:52

Published: Wednesday, 15 May 2019 01:39

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Vesta comes with the qflow package. Here we try to do a stand alone vesta installation, as it's very simple to do:

In dir where you have qflow downloaded, do this:

cd qflow-1.3.13/src

vesta.c, hash.c and hash.h are the 3 files used to generate binary vesta.

Copy these files + Makefile in some temporary dir, and generate vesta binary over there, so as to not mess the original qflow dir.

mkdir vesta_temp; cd vesta_temp; cp vesta.c, hash.c, hash.h, Makefile

Run Makefile in this dir to generate executable =>

make vesta

It runs this rule:

vesta$(EXEEXT): vesta.o $(HASHLIB)
$(CC) $(LDFLAGS) vesta.o $(HASHLIB) -o $@ $(LIBS)

These are the cmds seen on screen =>

cc -g -O2 -DPACKAGE_NAME=\"\" -DPACKAGE_TARNAME=\"\" -DPACKAGE_VERSION=\"\" -DPACKAGE_STRING=\"\" -DPACKAGE_BUGREPORT=\"\" -DPACKAGE_URL=\"\" -DSTDC_HEADERS=1 -DHAVE_SETENV=1 -DHAVE_PUTENV=1 -DTCLSH_PATH=\"/usr/local/bin/tclsh\" -DQFLOW_MAGIC_PATH=\"/usr/local/bin/magic\" -DQFLOW_NETGEN_PATH=\"/usr/local/bin/netgen\" -DQFLOW_QROUTER_PATH=\"/usr/local/bin/qrouter\" -DQFLOW_GRAYWOLF_PATH=\"/usr/local/bin/graywolf\" -DQFLOW_YOSYS_PATH=\"/usr/local/bin/yosys\" -DQFLOW_OPENTIMER_PATH=\"\" -DQFLOW_OPENSTA_PATH=\"\" -DQFLOW_VERSION=\"1.3\" -DQFLOW_REVISION=\"13\" -c vesta.c -o vesta.o

cc -g -O2  -DPACKAGE_NAME=\"\" -DPACKAGE_TARNAME=\"\" -DPACKAGE_VERSION=\"\" -DPACKAGE_STRING=\"\" -DPACKAGE_BUGREPORT=\"\" -DPACKAGE_URL=\"\" -DSTDC_HEADERS=1 -DHAVE_SETENV=1 -DHAVE_PUTENV=1 -DTCLSH_PATH=\"/usr/local/bin/tclsh\" -DQFLOW_MAGIC_PATH=\"/usr/local/bin/magic\" -DQFLOW_NETGEN_PATH=\"/usr/local/bin/netgen\" -DQFLOW_QROUTER_PATH=\"/usr/local/bin/qrouter\" -DQFLOW_GRAYWOLF_PATH=\"/usr/local/bin/graywolf\" -DQFLOW_YOSYS_PATH=\"/usr/local/bin/yosys\" -DQFLOW_OPENTIMER_PATH=\"\" -DQFLOW_OPENSTA_PATH=\"\" -DQFLOW_VERSION=\"1.3\" -DQFLOW_REVISION=\"13\" -c hash.c -o hash.o

cc vesta.o hash.o -o vesta

Or run this single cmd: cc -g -O2 hash.c vesta.c -o vesta => this will generate vesta executable

NOTE: for some reason, compilation shows error with this line when run as single cmd above (one of the defines -D is required):

vesta.c: In function ‘main’:
vesta.c:3795:31: error: expected ‘)’ before ‘QFLOW_VERSION’
  fprintf(stdout, "for qflow " QFLOW_VERSION "." QFLOW_REVISION "\n");
                               ^

Just comment out this line and compilation goes fine => //fprintf(stdout, "for qflow " QFLOW_VERSION "." QFLOW_REVISION "\n");

Now run vesta providing liberty file and netlist

./vesta map9v3.rtlnopwr.v /usr/local/share/qflow/tech/osu035/osu035_stdcells.lib => verilog netlist is the one generated by qflow after synthesis/PnR stage.

vesta.c:

main routine:

1. process cmd line arguments

2. Read liberty file => libertyRead(flib, &tables, &cells);

    liberty file table values get stored in linked list "tables" (struct lutable) and "cells" (struct cells)

3. Read verilog netlist => verilogRead(fsrc, cells, &netlist, &instlist, &inputlist, &outputlist, Nethash);

• Parse thru verilog netlist. Look for module/endmodule keywords for start or end of module.
• Then look for i/p, o/p pins and assign those i/o nets to inputlist (struct connect) and output list (struct connect).
• Then parser parses lines like this "CLKBUF CLKBUF_1 ( .A(clock), .Y(clock_buf4) );" Here CLKBUF is instance definition, and CLKBUF_1 is instance name. Both are parsed and instlist (struct instance) is created for CLKBUF_1, whose reference inst is CLKBUF. Then pin names A,Y are parsed and "struct connect" is created for each pin, here for "clock" with direction as i/p pin, and for "clock_buf4" with direction as o/p pin. netlist (struct net) is created for the nets connecting to these pins.

4. create internal links => createLinks(netlist, instlist, inputlist, outputlist);

5. Report on max delay paths

6. Report on min delay paths

5. Report on max delay paths

6. Report on min delay paths