Static Timing Analysis Flow

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Last Updated: Wednesday, 27 January 2021 06:05

Published: Saturday, 25 July 2020 03:07

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Static Timing Analysis (STA) Flow:

Once we have converted RTL to netlist, it's time to run Timing analysis on gate level netlist. When we have RTL, there is no concept of gates or delay. RTL is modeled as zero delay, so there is no delay, and as such no setup or hold times to meet. However, once this RTL is converted to gates, we have real delays for these gates. In order for this netlist to behave the same as RTL, all paths need to meet timing.

Static Timing Analysis commonly known as STA is the flow where we run a timing tool that analyzes all paths and finds out f there is any setup/hold violation on any of these paths.

Tools:

There are STA software available from both cadence and synopsys as well in open source world. PrimeTime (PT) from Synopsys is considered the gold standard for STA. Cadence has it's own tool called Encounter Timing System aka ETS. These are the 2 timing tools that are used by almost all the companies to run STA. From open source side, we have Vesta written by Tim Edwards. There is also another open source STA called OpenTimer. We'll discuss about each of these tools separately in their own sections.

STA timing corners:

STA requires running design at various corners. Recall that a tarnsistor's delay depends on PVT (see in solid state devices section for more details).

We run timing on max, min and typ corners. We run both "setup" and "hold" runs across all 3 corners (typ corner is optional, and many times just running max and min corner suffices)