setup and hold time

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Last Updated: Thursday, 27 July 2023 22:51

Published: Saturday, 18 July 2020 07:08

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Setup time  and Hold time:

Any logic you design from RTL, you will always hear about setup time and hold time, when running timing tools. Sequential elements such as flops and latches have setup and hold time requirements, in order to function correctly.Let's explore this important concept.

Origin of setup and hold time:

In broader terms, any circuit that stores value has a back to back inverter or some other back to back gates to hold the value. However such a circuit is not of much use, unless we can control the value that's stored in this back to back inverter. This is done via a signal to enable or disable the write, and another signal which transmits the value to be written into. This signal which enables or disables the write has a timing relation wrt to the signal that we are trying to write in. The value to be written in has to be stable around the time, the enable/disable signal changes, or else we may not store the desired value. This time window where we want our input signal to be stable is called setup time and hold time.

Setup time: The time before the enable signal that the input signal has to be stable

Hold time: The time after the enable signal that the input signal has to be stable

 The sum of "setup_time + hold_time" is the window where the input signal shouldn't change, or else the value stored in the seq element would be unpredictable.

This link does a superb job of explaining them:

https://www.edn.com/understanding-the-basics-of-setup-and-hold-time/

Setup and hold time in circuit paths:

We understand the setup/hold time of flops/latches, etc. But let's say we have a path from 1 flop to other flop. The 2nd flop can't have it's data change within it's setup/hold window.

Let's see a simple 2 bit counter. Violating setup time (too slow) or hold time (too fast) causes counter to have incorrect values as shown in the diagram.

Attach diagram FIXME

Eqn is:

That's why the 0 cycle path is called the hold timing for the path, as "hold time" of the capturing flop is involved in the eqn. Being a 0 cycle path, the freq of the clk has no impact on whether the path meets the "hold time". So, these paths are independent of freq.

Similarly 1 cycle path is called the setup timing for the path, as "setup time" of the capturing flop is involved in the eqn. Being a 1 cycle path, the freq of the clk will impact on whether the path meets the "setup time". So, these paths are dependent on freq, and setup time of the path can be fixed by relaxing the clk freq.

Timing Tools applying setup and hold time:

In PT and other timing tools, single cycle paths are easy to analyze. Usually paths are from flop to flop. So, most of the designs have 0 cycle hold paths and 1 cycle setup paths. When we have multiple clks with diff freq, then relationship gets more complex. Discuss MCP, and how setup/hold are calculated by timing tools