PT - multivoltage flow

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Last Updated: Sunday, 25 May 2025 01:01

Published: Wednesday, 14 October 2020 21:29

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Primetime Multivoltage flow

So far, we looked at Primetime Timing runs where we specified only one voltage domain, i.e all the libraries were specified with a single voltage. What if we have a design, where are multiple voltage domains. Some part of logic runs on Voltage A, while other runs on Voltage B.

PT can perform multivoltage analysis, where different cells in design can have different power supply. For this PT needs to know the power intent of design, which is in the UPF file.

Cmds for MV:

Instead of that, we can generate a PG netlist which has all pwr ports (VDD, VSS, VSUB, etc) of leaf instance (libcells will need to have these pwr ports in .lib). Pwr ports are in the netlist at top level too, and they get connected to these PG pins of leaf cells appropriately. Synthesis tools can dump out these PG netlists with correct pwr connections as specified in UPF. Now, it's lot easier to work with this netlist as UPF is not required aany more. All PG conectivity info is directly in the netlist.

Cmds in PT: