hardware description language - HDL

Details
Last Updated: Friday, 19 May 2023 22:33
Published: Monday, 11 December 2017 11:59
Hits: 3238

Hardware description language (HDL):

There are 2 most common languages - Verilog and VHDL to describe digital hardware. They are called as HDL. Just as we use C language to implement any functionality, we can use HDL to implement that function. We needed new language for describing hardware function, since languages like C aren't very conducive to describing hardware (however there are only few changes that are needed in C language to be a HDL like language. Infact, many compilers convert HDL to C language and then work on compiled C code to run simulation. Now languages like SystemC, an extension of C, are also used to describe hardware).

Just as C programs get compiled, HDL programs (describing hardware) also get compiled and generate assembly instructions. However for HDL, we also need a simulator which acts on this compiled code of assembly instructions, and generates responses which mimic real hardware behaviour. A lot of things work in parallel in real hardware which HDL mimics, and simulator takes care of this by running them in parallel (It still runs instructions sequentially, but gives impression of parallelism). This is where HDL differs from conventional languages. It needs a simulator, along with a compiler to generate results.

Verilog, VHDL and SystemVerilog are 3 common HDL languages.

1. Verilog:

CVC open source simulator (derived from GPL Cver) http://www.tachyon-da.com/

Verilog stuff: http://vlsicad.eecs.umich.edu/BK/Slots/cache/bawankule.com/verilogfaq/page2.html

This is the history of Verilog:

  • IEEE 1364-1995 (V1995): first generation of verilog. Gateway Design Automation introduced Verilog as an evolutionary HDL in 1985. It was purchased by Cadence and finally released to IEEE, which formed this std (IEEE Std 1364) in 1995.
  • IEEE 1364-2001 (V2001): Second gen of verilog. this std is most common, as it contains most of what modern verilog has.
  • IEEE 1364-2005 (V2005): 3rd gen of verilog. This just had minor corrections and few new language features (such as uwire keyword).


VPI: The Verilog Procedural Interface (VPI), originally known as PLI 2.0, is an interface primarily intended for the C programming language. It allows behavioral Verilog code to invoke C functions, and C functions to invoke standard Verilog system tasks. The Verilog Procedural Interface is part of the IEEE 1364 Programming Language Interface standard; the most recent edition of the standard is from 2005. VPI is sometimes also referred to as PLI 2, since it replaces the deprecated Program Language Interface (PLI). C++ is easily integrable with VPI (PLI 2.0), by using the "extern C/C++" keyword built into C++ compilers.

Verilog AMS:(analog and mixed signal) is a derivative of Verilog which extends event based simulator loops of digial simulation(V/SV/VHDL) by continuous time simulator. So, can simulate analog, digital and mixed ckt. It's a superset of digital Verilog HDL.

2. SystemVerilog:


Verilog was developed as a design language to mimic design spec, but was never inteneded for veriying the design. Verifying the design using Verilog constructs was difficult, and so "Superlog" language was created in 1998 to integrate verification features into the Verilog language and create the first hardware design and verification language.In 2003, Accellera approved SV 3.1.

  • IEEE 1800-2005 SV (SV2005): In 2005, SystemVerilog was adopted as IEEE Standard 1800-2005. This std is most common (3rd gen of verilog). SV2005 is a superset of V2005.
  • IEEE 1800-2009 SV (SV2009): In 2009, the standard from SV2005 was merged with the base Verilog V2005 (IEEE 1364-2005) standard creating SV2009. SV for design is an extension of Verilog-2005, while SV for test was mostly SV2005. Thus going forward, there was a single std and only SV-2009 was supported by all tools. No V2005 or SV2005 supported separately, as both design and test became part of SV2009.
  • IEEE 1800-2012 SV (SV2012): Error corrections and clarification of a few aspects of IEEE Std 1800-2009 lead to the release of IEEE Standard 1800-20012 known as SV2012.
  • IEEE 1800-2017 SV (SV2017): This is the current version as of 2023.

 

3. VHDL:


VHDL is not really that common anymore, and you may just bypass this language all together. You may need to learn it, incase you are working on old RTL that was coded in VHDL as VHDL was popular in the past. IEEE 1076-2002 (VHDL-2002) std most common, but latest is IEEE 1076-2008 (VHDL-2008).