verilog AMS
- Details
- Last Updated: Wednesday, 01 May 2019 13:46
- Published: Wednesday, 01 May 2019 13:46
- Hits: 2138
verilog-A & verilog-AMS:
-------------------------
both these languages don't support synthesis. They are used for simulation only to verify complex blocks.
Verilog-A:
--------
In face of competition from VHDL (an IEEE standard), which was absorbing analog capability from other languages (e.g. MAST) and evolving into VHDL-AMS, OVI agreed to support standardization of spectre behavioral language to add analog capability to verilog. However, OVI wanted to create Verilog-AMS \ a single language covering both analog and digital design. Verilog-A was an all-analog subset of Verilog-AMS that was the first phase of the project.
Verilog-A standard does not exist stand-alone - it is part of the complete Verilog-AMS standard. It is the continuous-time subset of Verilog-AMS. Spectre/TI-spice runs verilog-A, while ncsim runs verilog. Then results are combined. At top level, ncsim (or irun) is run on combined netlist. spectre is called as needed.
Verilog AMS:
-----------
Verilog analog and mixed signal (V-AMS) is a derivative of Verilog which extends event based simulator loops of digital simulation(V/SV/VHDL) by continuous time simulator. So, can simulate analog, digital and mixed ckt. It's a superset of digital Verilog HDL. It combines both Verilog and verilog-A, and then adds additional capability to allow description of mixed signal components.
The original intention of the Verilog-AMS committee was a single language for both analog and digital design, however due to delays in the merger process it remains at Accellera while Verilog evolved into SystemVerilog and went to the IEEE. Final plan is to pass accellera VAMS std to IEEE.
Verilog/AMS is a superset of the Verilog digital HDL, so all statements in digital domain work as in Verilog (see there for examples). We add electrical, analog, contribution (<+) as extra keywords in Verilog-A. Rest all syntax remains same as digital verilog.
NOTE:
1. Any module can have as many digital process, but only ONE analog process.
2. VerilogA can't have any digital signals (we can still have real/integer var). Every signal has to be analog. That's why we switch to Verilog-AMS since it allows us to use digital or analog for any i/p, o/p or internal signals.
3. cross, transition and bound_step are most needed functions to model in verilogA.
4. In irun, digital verilog only supports verilog 2001 or before. It can't support "always @*", nor any SV constructs as "#2ms". This is a limitation of irun. So, any vams file shouldn't have any newer verilog code.
Extra keywords added in Verilog-A:
--------------------------------
disciplines:
------------
Verilog AMS supports multiple disciplines. A discipline is a collection of related physical signal types, which in Verilog-A/MS are referred to as natures. For example, the electrical discipline consists of voltages and currents, where both voltage and current are natures. Verilog-A/MS by itself defines only one discipline, the empty discipline, and it defines no natures. Thus, in order for the language to be able to describe models that operate on physical signals, the disciplines and natures associated with those signals must be defined. A collection of common disciplines and natures are defined in a file disciplines.vams that is provided with all implementations of Verilog-A/MS.
natures: specifies attributes of signal type
------
nature Voltage
abstol = 1u; //absolute tolerance in real number
units = "V";
access = V; //access function name that we use in verilogA to get voltage of a node. Note capital V used, so using small v to get voltage of a node won't work
endnature
nature Current
abstol = 1p; //absolute tolerance in real number
units = "A";
access = I; //access function name that we use in verilogA to get current b/w 2 nodes
endnature
disciplines: combines 2 natures to define potential/flow pair. One gives type for potential(voltage) while other for flow(current)
--------
discipline electrical
potential Voltage;
flow Current;
enddiscipline
discipline voltage //we use separate voltage discipline where currents are not needed. saves computation time
potential Voltage;
enddiscipline
ex:
electrical in; //in can take both voltage and current value
voltage out; //out can take only voltage value but not current. electrical and voltage ports can be connected directly.
mixed signal behaviour can be modeled from models which are built from purely digital and analog blocks, and these models can be freely interconnected with VAMS automatically performing the signal conversion.
discipline are not part of verilog, but were introduced in verilog-A for cont time signals. VAMS extended this concept to digital signals also, but disciplines were made optional for these discrete time signals by having default discrete time discipline as "logic", which is defined in discipline.vams.
discipline logic
domain discrete;
enddiscipline
NOTE: logic in VAMS is diff than one in SV. It just says that these signals are not electrical, but digital 0/1.
VrilogA vs VerilogAMS: Since i/p, o/p signals in VerilogA can only be electrical, modeling digital signals in Verilog-A is difficult (see ex of nand gate on pg 71 of Designer's guide notes). Use Verilog-AMS instead. In verilogAMS, we can write digital code within analog block, so it's much easier to model digital signals.
probe: to probe voltage or current. If branch is empty, current probe shorts the branch, while voltage probe causes open ckt.
---
These below stmt don't need to be in "analog block". They can be anywhere (i.e in digital always too) in vams file.
real x; x=V(a,b); //x gets voltage b/w a and b
real x; x=I(a); //x gets current b/w a and ground. Everything is referenced in any schematic wrt ground. So, we need to have a ground node or else everything is floating. We provide gnd! on one node, then all nodes are solved wrt this node. If we do not provide gnd node, then tool can't solve as there will be infinite soln for node voltages. (i.e tool can choose gnd node at 1V, 2V, etc and all other node voltages will change based on that). ground node is provided as follows:
electrical gnd;
ground gnd;
$cds_iprobe => to probe volt/cur at any node. Can be used only inside "analog block"
real x; x=$cds_iprobe("TB.I0.net1); => this puts a current probe and continuously assigns value on net1 to var x.
NOTE: all signals in regular schematics of transistors are electrical (since transistors are verilogA models with electrical input/output). So, we can probe any of these signals same way as we can probe any signal in Verilog-A.
Simvision:
--------
1. A/D signals: On simvision gui, the way to know if a signal is digital or analog is to look at signal icon whenever we see at signal list to choose. If it shows a pulse type, it's digital, while if it shows sine wave, it' analog. If we see *_$flow as signal name, it represents a current for that signal as opposed to voltage.
NOTE: If a signal comes from srcVerilogAMS model, it's digital (0/1), while if it comes from schematic, it's analog (V/I). If a digital goes into analog or vice versa, D2A or A2D connect modules are placed. Depending on whether they are placed on o/p pin of 1st gate or i/p pin of next gate, the signal may show up as an analog or digital signal in waveform viewer. Only when both 1st and 2nd logic are both analog or both digital, only then the signal will show up as only analog or only digital. At interfaces of analog and digital, tool tries to keep digital signals as much as possible to save on sim time.
2. timestep: To know the timestep for analog signals, we can display any anlog signal on waveform. Then right click on signal value (where it shows the voltage/current number). then click on symbol->Points & Lines. Then click on triangle or plus, and it will show the all the points where analog values were calculated. This is a good way to see how tool is working with analog signals.
AMS simulator: see "running AMS" section in cadence_virtuoso.txt
-------------
See also in simulation.txt for probe of ams signals.
type:
----
We have signals as electrical/voltage type, and variables as integer/real type.
ex: real [3:0] vout;
reg [5:0] gain; real vgain; vgain = pow(10.0,(gain-32.0)/20); //here if we use integer 32 instead of real 32.0, then we get convergence error during sim complaining it's NaN. This happens because result of operations on unsigned registers/nets is unsigned. Here gain is unsigned, so when gain=0, then gain-32=-32 which is 0+(-32)=32'b0+32'b111...11100000=32'b111...11100000. However, since the result is supposed to be unsigned, this result is treated as unsigned number. Then this unsignned number represents 2^32-32=4294967296-32=4294967264. This is a huge +ve number which causes vgain to be infinite, and hence convergence issues. Use real as one of the inputs, which makes the result real, which is signed. Another soln is to assign reg "gain" to integer which is signed by defn, and then perform "-" which gives signed result.
wreal: wire with real value on it. This is useful as it can be used in digital block instead of using analog block
ex:
wreal out; real result;
assign out=result; => usually real number can be assigned to out in analog module (analog V(out) <+ result;)
wire porz; wreal VDD;
assign #10 porz = (VDD > 1.2) ? 1'b1 : 1'b0; => This converts from real to signal. very useful
expressions:
----------
1. If else: A ? cond1 : cond2; if (V(in) > 0) V(sw) <+ 0; else I(sw) <+0;
2. case: case (a) 0:.. 1:... endcase
3. for: for(i=0;i<=10;i=i+1) begin ... end
4. while: while(i<bits) begin ... end
Events: they force simulator to place time points at events, else simulator may miss that time point, and results may vary from run to un.
-----
@blocks : blocks of code executed upon an event. These are non-blocking so other smt can proceed.
analog begin
@(initial_step or final_step) begin //simulator places time point at initial step and final step, and assigns hold to V(in) at that time
hold=V(in); //since hold is variable, it retains it's value over time. So, initial value of hold is retained until the end.
V(a,b) <+ 5; //since V(a,b) is electrical and assigned using <+, it is evaluated only at initial or final step. At other times, it's not evaluated, so, it's X or floating.So, <+ operator should not be used within event (@).
end
@(timer(Tstart,T)) //creates events every t=Tstart+kT, where k=0,1,2,..
@cross(V(in),+1) //places event when V(in) is rising (-1 for falling, 0 for either) just after the crossing within tolerances. NOTE: V(in) needs to go from -ve to +ve for it to detect event. If V(in) goes from 0 to 1V, then cross never happens.
; //It's placed simply to assure edges are not missed. Very imp to place it at start of every "analog" block.
end
always @above(V(in)-Vmax, 1n, 1m) $display("MAX exceeded"); //this looks for arg to be above 0 (V(in) >= Vmax) within 1mV tolerance, and a time delay of 1ns. NOTE: this is not within an "analog begin end" block, but is an always block as if in digital. This works !!
transition filter: converts piecewise constant signal to PWL signal. Can only be applied to piecewise constant and NOT to continuous signals.
-----------------
Out = transition(In, td, tt); //adds td delay to "In" signal with rise/fall time of tt. If different rise/fall desired, then ad 4th arg, i.e:
Out = transition(In, td, tr, tf); //NOTE: out is a "real" variable, and not a signal. IN shouldn't vary continuously, i.e it should be any voltage/current in analog domain
V(mid) <+ transition(en, 1n, 10n)*V(vdd); //causes "en" to rise/fall with 10ns time, delay of 1ns and goes from rail to rail. This stmt converted a digital signal (en) to analog signal (mid). NOTE: <+ is needed, since this needs to be evaluated continuously. So, needs to be in "analog begin .. end" block.
NOTE: transition stmt is used to ramp up power supplies:
ex:
real vsys_r =0;
electrical out;
initial begin
#0 vsys_r = 0;
#100 vsys_r = 1.8;
#100 vsys_r = 1.2;
end
analog begin
V(out) <+ transition(vsys_r, 10u, 1u);
end
contribution:
-------------
In analog domain, some new operators are defined, for example the "<+" branch contribution operator. It's called contribution operator, because it keeps on adding contributions.
For ex: A <+ 1; A <+ 2; will assign final value of 1+2=3 to A. A simple assign would have assigned value of 2 to A.
A contribution statement takes the form of a branch signal on the left side of a contribution operator, e<+f, followed by an expression on the right side. The branch signal on the left side is forced to be equal to the value of the expression at all times. So, it's different than other languages in the sense that it solcves differential eqn to arrive at a soln that satisifies this. So can be time intensive.
1. Ex of Resistor: V=I*R: model below models a liner resistor
-----------
`include gdisciplines.vamsh // It defines names V and I which are used in the model below.
module resistor (p, n);
parameter real r=0; // resistance (Ohms)
inout p, n; //port dirn is bidir (ports are optional as they aren't used in verilog-a/spice simulation)
electrical p, n; //type of port is electrical (electrical is a discipline), meaning signals associated with the ports are expected to be voltage and current.
//branch (p,n) res; //optional to specify branch. This gives more concise code, as we can use V(res) instead of V(p,n) below.
analog // analog says that it's an analog process, which describes continuous time behaviour (similar to always).
V(p,n) <+ r * I(p,n); //contribution stmt that defines relationship b/w voltage across branch b/w "p and n ports" and current flowing thru the branch b/w "p and n ports".
//I(p,n) <+ c*ddt(V(p,n)); => for cap (ddt=time derivative, idt=time integral of its arg)
//V(p,n) <+ l*ddt(I(p,n)); => for ind (idt used for integral, not needed here)
//for more than one stmt in anlog section, use "analog begin .... end" stmt.
endmodule
resistor #(.r(50)) Rload (out, gnd); //instantiates a 50 ohm resistor
-----------------------
2. Ex of inverter:
-----------------
include gdisciplines.vamsh
module inverter (q, a);
output q;
input a;
wire a, q; // digital net type (declaration optional)
logic a, q; //discipline for a,q default to "logic" when not defined. So, this stmt optional
assign q = ~a; //cont assignment
endmodule
3. Ex of sinusoid wave:
-------------
module sinwave(out);
output out; electrical out;
parameter real freq,phase; //these can be set wherever this module is instantiated
analog begin
V(out) <+ sin(2*`M_PI*(freq*$abstime + phase/360)); //$abstime returns time in seconds.
$bound_step(0.1/freq); //specifies max time step that can be taken. else simulator may choose very large timestep exactly at same point every cycle that will still satisfy above eqn. $bound_step is usually needed for indep src which produce repetitive o/p with no i/p. This specs 10 timesteps every sinusoid, enough to generate smooth curve. For 1MHz sinewave, we'll see 100ns timestep on ams simulation.log window. But tran time on log window will show results every couple of steps, so that every 5% of simtime we see tran time and other info. That has nothing to do with timestep. step size shows in last 2 columns.
end
endmodule
NOTE: In verilog (digital), we can model a sinewave with real numbers, by inc time step in a for loop. see system_verilog.txt for ex.
4. module instantiations: we do it in same way as in verilog. By default, nets are electrical.
--------------
module das_top(ind, in0, in1, out0, out1);
logic ind; //specifies tha this is digital signal
electrical in0, in1, out0, out1; //specifies tha these are analog signals.
diffamp Idiff0 (in0, out0);
diffamp Idiff1 (in0, out1);
endmodule
5. mux in verilog-AMS: note: digital signals are freely used inside analog block (unlike in verilog-A). so easier to model digital. Make sure events are synchronized b/w digital and analog, else edges might be missed, since analog and digital have different time steps.
-----------
module (in0,in1,out,sel);
input in0,in1; electrical in0,in1; //analog signal, so electrical. nature "electrical" of signal is figured out automatically by tool, depending on who's driving it
input sel; logic sel; ///digital signal, voltage levels for digital signals are still unknown here, but we don't need them
output out; logic out; //digital signal, nature "logic" of signal is figured out automatically by tool, depending on who's driving it
real gain; //this variable cab shared b/w analog and digital modules
always begin //digital block
gain = V(in0)*20; //since var gain is assigned value in digital, digital owns it and analog block may only read it, but not modify it. Note: electrical signals can be read into digital and assigned to int/real to be used
@(vgain); //we need @ stmt or else this always block gets into infinite loop
end
always @(cross(V(in0,in1),+1) count = count+1; //digital block. analog cross function can be used in digital
analog begin //analog block
@(posedge sel or negedge sel) //we need separate posedge and negedge, else tool complains. In pure verilog, we could do @(sel), but not here. This is limitation of AMS-Designer tool
; //forces time step at edge of sel signal. Any digital signal from digital block can be read into analog block. We synchronize analog kernel to avoid missing edges. However if sel signal is not wire/reg, but integer/real, then we need to do it as in pg 121 of Designer's guide book
V(out) <+ V(in0)*(transition(sel==0 ? 1 : 0),0,1n); //sel=0
V(out) <+ V(in1)*(transition(sel==1 ? 1 : 0),0,1n); //sel=1
end
endmodule
6. DAC in verilog-AMS:
--------------
`timescale 1s/1ps => we should give 1s as timescale in digital modules also, as analog blocks always use 1s as timescale, so both digital and analog will remain in sync. Very important to do this and use #delay carefully as they have 1sec as timescale
module dac(in, out,clk);
input [5:0] in; //in can take digital codes from 0 to 63
input clk;
output out; //no need to define electrical or logic as tool figures it out
real result;
analog begin
@(posedge clk)
result = in/63; //result varies from 0 to 1
V(out) <+ transition(result,0,10n); out varies from 0V to 1V
end
endmodule
7. AND gate in verilog-AMS in TI library (AN210 srcVerilogAMS file)
-------------
`include "disciplines.vams"
module AN210 ( A , B , Y , VDD, VSS); //NOTE 2 extra pins VDD and VSS added. There's also srcVerilog file which doesn't have these vdd/vss pins
electrical VDD; electrical VSS;
input(* integer supplySensitivity = "VDD" ; integer groundSensitivity = "VSS" ; *) A; //pins voltages are VDD/VSS for 1/0
input(* integer supplySensitivity = "VDD" ; integer groundSensitivity = "VSS" ; *) B;
output(* integer supplySensitivity = "VDD" ;integer groundSensitivity = "VSS" ; *) Y;
and #0 TI_AND_PRIM0 ( Y , A , B ) ;
endmodule
8. analog switch in verilog-AMS:
-----------
module sw_ana (vin, control, vout); //control connects vin to vout
inout vin, vout;
electrical vin, vout; //analog
input control;
logic control; //digital (this should be digital (piecewise constant) else can't be used in transition filter below)
parameter real Ron=1, Roff=10M; //parameters that can be changed from outside
real rout; //local variable
initial begin .. end //digital process
always @(...) begin .. end //digital process
analog begin
Rout = Ron/Roff * pow(Ron/Roff, transition(control, td, tr, tf)); //log func implemented for contonuously varying resistance from on->off or off->on. Note: here it's = sign (not <+ sign). If control signal can be "high z" or "x", we can add internal signal that forces "control_int" to 0, whenever control is anything other than 1 by writing this code as separate digital process => always @(control) if (control == 1'b1) control_int=1'b1 else control_int=1'b0;
//Rout = Roff + ((Ron - Roff) * transition(control, td, tr, tf)); //linear func instead of log func above. simplistic but not accurate in how switches work.
I(vin, vout) <+ V(vin, vout) / Rout; //solves for V,I with resistor in between nodes vin and vout
end
endmodule
9. Fuse model: fuse is a resistor with 2 pins: P, M (used in silverfox, since fuse needed vams model)
----------
module FUSE_WRAPPER(M, P);
inout M;
electrical M;
inout P;
electrical P;
localparam real rblown = 700000 ;
localparam real rfuse_initial = 50;
integer numCross;
real t1, t2;
localparam real iBlow = 35e-3 ;
real rfuse ;
integer status;
analog begin
@(initial_step("tran")) begin
numCross = 0;
t1 = 0 ;
t2 = 0 ;
$display("INSTANCE PATH :- %m");
rfuse = rfuse_initial;
$display("VALUE OF RFUSE IS %f",rfuse);
status = 0;
end
@(cross(I(P,M)-iBlow,1)) begin //rising edge of current
if (numCross == 0 && status == 0) begin
numCross=numCross+1;
t1 = $abstime ;
end
end
@(cross(I(P,M)-iBlow,-1)) begin //falling edge of current
if (numCross == 1 && status == 0) begin
numCross=numCross+1;
t2 = $abstime ;
end
end
if (numCross == 2 && status == 0) begin //check how long current remained high. If met time spec, then blow it.
if((t2 - t1) > 300e-9) begin // make 300ns per design team
rfuse = rblown ;
status = 1;
$display("IN INSTANCE PATH :- %m");
$display("PROGRAMMED :- %m");
end
end
V(P,M) <+ rfuse*I(P,M) ; //rfuse_unprog=50ohms, rfuse_prog=700Kohms
end //analog end
endmodule
10. Write top level TB for design:
-------------------------------
A. Create top level schematic. Instantiate sdtimulus block, and DUT block and connect pins as needed.
B. Create verilogams view of stimulus block. Write code to Drive stimulus to DUT (DUT is schematic for SilverFox or some other top level chip block)
--
creating a verilogams view of stimulus providing block:
`include "constants.vams"
`include "disciplines.vams"
module TOP_stim (A, VDD_TX, VDD_RX, VIO_OUT, VSS, Y, Z); //VDD_* are supply to blocks inside DUT, while VIO_OUT is supply to IO pad of DUT.
input VSS;
input (* integer supplySensitivity = "VIO_OUT" ; integer groundSensitivity = "VSS" ; *) A; //indicates pin voltages for i/p pin A
output (* integer supplySensitivity = "VIO_OUT" ; integer groundSensitivity = "VSS" ; *) Y; //indicates pin voltages for 0/p pin Y
output Z; //output pins can also be w/o any SS.
output VDD_TX, VDD_RX, VIO_OUT;
electrical Z;
electrical VDD_TX, VDD_RX, VIO_OUT, VSS; //all supplies defined as electrical
parameter real Vtx=0.0, Vrx=3.3, Vio=1.8, I_PD1; //specified as parameters so that they can be modified from other testcase module.
reg A, Y, Z;
reg [7:0] data, etc;
reg [255*8:0] sim_description; //to display test name on waveform viewer
//instantiate other modules
switch_ana (* integer library_binding="SILVERFOX_TOPSIMS"; *) reset_sw (dut.RST, RST_SW, dut.VIO); //this adds an additional connection b/w VIO and RST pin of DUT. This helps us drive VIO on RST pin by controlling RST_SW signal.
//include testcase file which has digital initial process
`include "/db/.../fuse_tc.vams"; //explained in separate section below
//digital initial process
initial begin
$sdf_annotate(...); //for max/min
Y=0; Vtx=0; //NOTE: reg Y is written as 0 instead of 1'b0. That's valid as verilog treats this as 32 bit decimal and uses lsb of "32'd0".
#5 Y=1; Vtx=5.0;
end
//analog process (runs at every timestep)
analog begin
I_PD1 = $cds_irprobe("ams_TOP.DUT.PD[1]"); //This is convenient way so that current can be displayed anytime desired in testcase, by displaying this variable. Else we'll need to include it in irun cmd line to dump current at that level of hierarchy.
//to ramp up power supply
V(VDD_TX) <+ transition(Vtx, td, tr, tf); //since Vtx is real and piecewise constant, transition func works on it.
//to display thermal shutdown event
@cross(V(ams_top.TSD)-0.7,0) begin
TSD_temp = $temperature-273; //records tsd temp
//vrx = V(VDD_RX); //record supply voltage
$display("TSD temp = %g", TSD_temp); //%g is is used to display real var (can also use %f, %r, %e")
end
end
endmodule
fuse_tc.vams:
---
real diff; //any new var defined here
initial begin
SCK =0;
#5 LED=0;
#1_000_000;
Vtx=2.2; //Vtx is changed so analog block in stim file above causes V(VDD_TX) to ramp down to 2.2V.
force ams_TOP.nPUC = 1'b0;
spi_read(...);
diff = V(ams_TOP.SILVER.I1.SH_OUT1) - V(ams_TOP.SILVER.I1.SH_OUT2); //analog sigs can be accessed directly in this digital block
$finish;
end
--------------------------