Bus Architectures

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Last Updated: Monday, 29 August 2022 23:36

Published: Wednesday, 25 March 2020 00:55

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Bus Architectures:

This section lists the most popular bus architectures in existence today. All chips use some form of bus protocol to communicate between different blocks on the same chip, or to talk to other chips. Bus are simple physical wires that connect one chip to the other. So, the first question we might have is why are there so many different kinds of buses when ultimately they all just transfer signals over the same kind of physical wires. Won't they all perform more or less the same, and achieve the same result. That's true. For the physical part, wires don't change their physical transmission capabilities based on bus protocol. The difference in performance between these different buses come mainly due to the software part: how the bus protocol is designed, how much of the work is being in software vs hardware, how scalable the protocol is, etc.

This is how a new bus architecture gets introduced. There is a bus architecture that's proposed by a company or a group of companies. If it gains enough traction, it' starts getting implemented in devices.This is how all basic buses work. When we connect 1 device to another, data xfer takes place between them. It's based on a protocol, that defines how the receiver and the sender transport data and interprets them. For ex, when we connect HDMI cable on back of HD TV to a DVD player, the DVD player and the TV talk using this HDMI protocol on that cable. That protocol defines exactly the cmds and data sequence to be followed. Many of these standards are from old times, and doesn't have any patents or owner. However, many of the recent protocols are properitery, and if you want to use them in your chip, you have to pay a royalty to the owner. You can also have your own protocol, since what is needed is basically a clock line and a data line, and you can have the simplest protocol, and have the bus be called based on your "name". Note that all these bus protocols refer to digital buses, as we use the buses to xfer 0's and 1's.

We'll look at the brief history of various bus protocols:

1st generation bus: These were simple buses as MCA, ISA, EISA, VESA bus.

2nd generation bus: These were more complicated buses, but had more functionality and achieved better speeds. These buses include PCi, AGP, PCI-X, etc.

3rd generation bus: These were radically changed design to take advantage of improvements in physical wire transmission capabilities, and could achieve clock speeds in GHz.  PCI Express, HDMI etc fall in this bucket.

Serial Vs Parallel Bus Architectures:

Parallel bus architecture: In the early days, we had parallel bus architecture, and that is what 1st and 2nd generation buses used. Parallel bus architecture is one where different bits of a bus are transmitted in parallel. They are all transmitted on a clock edge, and then received on next clock edge. This architecture made sense as more the bits you transfer in parallel, higher your throughput would be. This worked for clock speeds up to 500MHz or so.

However, in early 2000, there were significant advances in bus technology wrt phyical layout, transistor design, etc which allowed for much higher speeds ( > 1GHz). Parallel bus architecture wasn't suited for these very high speeds. Multiple reasons for this:

1. Cross talk between adjacent parallel data lines: Data signal travelling over one data line corrupts data in adjacent line. This is OK for low speeds, but at high speeds, capacitance behaves like a short circuit, so signal on one line basically starts traveling on adjacent line too. One solution is to space out parallel lines, but that takes more area, and hence higher cost.
2. Skew between various bits: As number of bits in bus increased, there were more lines in parallel. They all need to remain within a certain skew, i.e one bit of a bus can't arrive much earlier or much later than all the other bits of the bus. They all have to arrive at the same time, in order to achieve high speed. If they arrive skewed with each other, then clock speed has to be reduced by the skew amount to allow all bits of the parallel bus to be captured correctly. This put a limit on the number of bits of a bus that can be sent out in parallel.
3. ElectroMagnetic interference (EMI): This is unwanted interference when high frequency signals are transmitted. These radiate energy, and can couple to other signals and distort their waveform. One way to prevent EMI from disturbing your signal is to shield your signal in cyclinderical wire  shield. However, doing it for all wires of the buses becomes expensive.

Serial Bus architecture: Serial bus architecture got rid of all these issues. However, it required a much higher clock speed to maintain same throughput as parallel bus architecture. In fact, if we had 16 bit parallel bus running at 500MHz in parallel bus, then for serial bus, we needed 16*500=8GHz clock speed to maintain same throughput. This is very speed clk, but now there is no issue of cross talk or skew as there were no adjacent lines in parallel bus. EMI is still there, but can be mitigated by shielding wire (as there is only 1 wire, it's much simpler now).

SERDES in serial bus architecture: Internally on chip, data is transferred in parallel, but just before it comes to pads of the chip, it's converted to serial data. It's transferred as serial 1 wire data on the motherboard, and goes to the pads of the other chip as serial data. Right after the data enters the pads of other chip, it's again converted to parallel data. Why do we do this conversion? i.e why not just transfer data serially all the way. The reason is that parallel data is still faster and requires much lower clock speed. Most of the problem that we had with parallel data transfer was on motherboard, where it's harder to manage crosstalk and skew. This logic on transmitting side chip, that converts parallel data into serial data, is called serializer (or SER). Similarly, This logic on receiving side chip, that converts serial data into parallel data, is called deserializer (or DES). Both of these components combined are called SERDES (serializer deserializer). You will hear this term a lot with all serial bus arch.  Most of the modern bus architectures are all serial bus architectures, and are also called SERDES arch. There are also Equalizer circuit on both TX and RX just before the chip pins connect to the cable/channel. These Equalizers are needed since cable starts attenuating the signals at low freq, but we need to transmit signals at much higher freq. Equalizers on TX side boost the signal Bandwidth, so that even after attenuation. the signal maintains it's signal levels at hugher freq, which can then be recovered by the RX equalizer.

A full diagram of SERDES logic is shown below. FIXME attach picture belo:

There's a very good video lecture on youtube: (by "analog layout and design")

https://www.youtube.com/watch?v=FGzQV4a9KAw

PIPE (Phy Interface for PCI Express and USB SuperSpeed Architecture):

There are many SERDES bus architecture is use such as USB, DDR, PCIe, etc. They all have same kind of design: an analog phy that has the TX/RX, a digital controller that communicates with the analog Phy, and then software and device drivers that interact with the digital controller.

PIPE: Comes PIPE, which is a spec developed for Phy interface. This is to enable development of a phy as a discrete IC or as a macrocell for inlcusion in ASIC designs. It defines a standard interface between such a PHY and a Media Access Layer (MAC) & Link Layer ASIC. One of the motivations behind Phy and digital i/f is that Peripheral and IP vendors will be able to develop and validate their designs, insulated from the high-speed and analog circuitry issues associated with the PCI Express or USB SuperSpeed PHY interfaces, thus minimizing the time and risk of their development cycles.Though PIPE refers to PCIE Express in it's name, it's applicable to USB too. Below is the pic of a PIPE i/f.

Common Bus Architecture and Protocols:
 

There are many serial nThese are some of the common Bus Standards in use today:

SPI and I2C are not only the 2 oldest bus standards, but also the simplest. They are still widely used today amongst 2 chips to transfer data betweenthem.

SPI: This is a 4 wire bus protocol. Very simple design. Widely used as simple communication interface between 2 chips.

I2C: This is a 2 wire interface. It's slightly complicated, but advantage is that it only uses 2 pins, so reduces overall area and cost.

USB: Uiversal Serial Bus. Most common bus interface that you see in all devices.

PCI: Peripheral Component Interconnect Bus. Another very popular bus format

HDMI: Mainly used to transfer audio/video signals from one electronic device to another for display purposes.

 MIPI:

DDR: