PCI - Peripheral Component Interconnect Bus

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Last Updated: Thursday, 02 September 2021 00:13

Published: Tuesday, 23 March 2021 22:55

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PCI Bus:

PCI is a 2nd generation bus standard that was developed by Intel in 1990. By 1994, PCI became widely used in Pentium PCs. PCI-X which was an enhanced version of PCI was released with faster speeds. After PCI and PCI-X, came the enhanced PCI Express (or PCIE) which was the 3rd generation bus standard, with much faster speeds. This is what we have today in all modern devices. Original PCI and PCI-X are almost non existent.

There were multiple PCI standard as PCI 1.0 (5V signaling), PCI 2.0 (3.3V signaling, PCI-X) and PCI 3.0 (PCIE).The 2nd generation buses were PCI and enhanced version of PCI called PCI-X. The third generation of PCI is what we have today known as PCI Express (or PCIE). We'll look at 3 standards: PCI, PCI-X and PCI Express. like any other bus standard, PCI main objective is to transfer data between devices at highest rate possible.

Spec:

PCI 1.0: PCI bus originally had 33.33MHz clock with synchronous transfers. They had 32 bit wide bus, which gives it a peak transfer rate of 4byte*33.33=133MB/sec. It's 5V signalling, though 3.3V is also supported. It allowed multiple devices to share the same bus, which put a limit on the maximum frequency the bus can support. Clock speed of 33.33MHz (i.e time period=30ns) was only able to support 4-5 slots per bus, as beyond that load would be too high to meet timing. PCI later increased clock speed to 66MHz, which allowed only 1-2 slots per bus.

PCI 2.0: Later PCI-X came with 66MHz and 133MHz clock speeds, with more slots per bus.

PCI connector:

There are PCI connector cards which have contacts on each side of the connector. They have few notches to make sure that they fit only where they are compatible with the voltage supply (5V or 3.3V).

PCI bus transactions:

PCI bus traffic consists of a series of PCI bus transactions. Each transaction consists of an address phase followed by one or more data phases. The direction of the data phases may be from initiator to target (write transaction) or vice versa (read transaction), but all of the data phases must be in the same direction. Either party may pause or halt the data phases at any point.

Each PCI bus transaction

a local computer bus that attaches hardware devices in a

PCI Express:

Documents:

This by mindshare is a good one:

https://www.mindshare.com/files/resources/MindShare_Intro_to_PIPE_spec.pdf