eco - Cadence Conformal
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- Last Updated: Friday, 19 June 2020 03:38
- Published: Friday, 12 October 2018 04:31
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ECO Flow:
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Many types of ECO flow supported in Encounter L/XL/FE-L/FE-XL (Enc version 7 and above). GXL and conformal ECO have additional support for ECO. GXL supports ecoRemap, while conformal supports conformalECO.
These ECO flows supported in Enc:
1. Pre-Mask changes from ECO file => note: eco file generates a new verilog netlist, which is used by subsequent steps.
2. Pre-Mask changes from new verilog netlist =>
loadConfig old.conf, set rda_Input(ui_netlist) "newchip.v", ecoDefIn oldchip.def, ecoPlace, ecoRoute, ..
3. Pre-Mask changes from new DEF file => similar as 2 above, as def file contains new logical cells/connections. An ECO file is generated by ecoCompareNetlist, loadECO loads this eco file, and then follow as in 2.
4. Post-Mask changes from new verilog netlist => use -postMask for ecoDefIn to minimize mask changes. Otherwise same as pre-mask.
5. Post-Mask changes using ECO spare cells or GA(gate array) cells. => preferred method at TI
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2 methods for generating new eco netlist: (we've the new 1p1 rtl with our fixes in)
1. Manual: Here, we look at 1p0 netlist in debussy and figure out where to place gates in 1p1 netlist. Then, we an modify netlist in 2 ways: (In both of these ways, new netlist only has new gates added with appr connections. These new gates are not connected or matched to spare gates as the VDIO tool is supposed to do those connections).
A. eco directive file: create eco_directive file that has the list of gate changes and connections. What this does is that it adds new gates with appr connections to netlist. We should look at this new netlist generated before we move to VDIO. Then we read in this file in VDIO.
B. directly modify old ntlist: We directly modify old netlist and then read in the new netlist. This new netlist has new gates added with appr connections. It's similar to above option except that we don't use eco directives.
Then we run VDIO which reads in the old def and the new netlist (either eco directive or new verilog netlist). The tool then matches the changes with spare gates, places them and routes it to create lec clean netlist and def. then we run final checks, timing, etc. We discuss this methos below.
2. Conformal: Here we use conformal lec. We modify rtl for 1p1. Then we run thru Synthesis to create 1p1 netlist. Then we run conformal lec which diffs old 1p0 PnR netlist with newly synthesized 1p1 netlist. It creates a patch, and then generates a new netlist with the changes. This new netlist uses spare cells, so spare cells are already mapped to new logic within netlist (you'll see that spare cells are removed from the spare module). In manual option above, no spare cells were mapped to new logic. Then we go thru regulat PnR flow to accomodate this patch in VDIO. We dsicuss this method in later section marked conformal_eco.
NOTE: Regardless of which method we use for generating netlist, we have to run ecoDesign in VDIO (super cmd which does everything for us). We can also make changes directly to verilog and run ecoDesign.
#ecoDesign cmd is supported in all Enc version, so use ecoDesign. It takes EDI System database and a modified netlist as input and performs ECO operations. It restores the design, examines the changes in the new netlist, and automatically implements the required changes with ecoPlace and ecoRoute. deffile is not there in enc.dat database, but it's OK as rout.gz and place.gz has that info.
ecoDesign -postMask -modifyOnlyLayers <MLb>:<MLt> -spareCells <spareCellName> -useGACells <GACoresite> <old_design.enc.dat top_cell new_netlist> => Use -noEcoPlace -noEcoRoute if we don't want to ecoplace and ecoroute with this cmd, but want to do it separately.
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Manual ECO (non conformal):
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Inreactive ECO: provides manual inc updates to design.
#we can also do an interactive ECO by going to optimize->interactive ECO for PreMask changes. We can add repeater(ecoAddRepeater), upsize/downsize instances(ecoChangeCell), delete buffers(ecoDeleteRepeater), display buffer tree to modify it(displayBufTree)
#For PreMask/PostMask ECO, we can also do file->ECO design. Then goto Place->ECO Place for placement. then do routing by route->Nanoroute (choose ECO route) => instead of doing it on the encounter cmd line
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ECO changes using ECO spare cells (post mask):
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Flow for Making changes from ECO file: (preferred method at TI)
load old config file => load new_change.eco file (modifies old verilog to get new verilog) => ecoDefIn old_def file => specifySpareGate => ecoPlace => ecoRoute =>save design
#0. make new(1p1) dir and cp files from old(1p0) dir & then change mode:
cp -rf /db/YELLOWSTONE/design1p0 /db/YELLOWSTONE/design1p1
chmod 777 -R /db/YELLOWSTONE/design1p1
1. Update RTL in Source dir.
#run debussy in old dir on gate level netlist to look at gates to make changes in gate level netlist
cd /db/EPSTINGRAY/design2p0/HDL/Debussy.
Run create_symbols if *.lib++ dir not present
run_debussy => runs debussy with/without any options. If with options, "-f <gate_netlist>". If w/o options, bring up debussy, click File->Import design, Put the file name (/db/DRV9401/design1p0/HDL/FinalFiles/digtop_VDIO.v) in bottom box, and then click Add, then OK.
2A. Run ECO flow in VDIO after running encounter (tcl/eco_flow.tcl => this file has all cmds in it for eco flow)
NOTE: to add/delete any pins, use PinEditor in VDIO gui (Edit->PinEditor). Do this before running ecoplace. Else, new pins are added at origin (0,0). To edit/add pin, you can also use "editPin" cmd:
#editPin -pinWidth 0.4 -pinDepth 0.4 -fixOverlap 1 -side Left -layer 3 -assign 0.0 367.85 -pin RX_SEL[4]
1st option: run ecoDesign with no place and route. This super cmd is explained above.
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ecoDesign -postMask -noEcoPlace -noEcoRoute -spareCells spr_*/spr* dbs/filler/filler.enc.dat digtop /db/HAMMER_OA/design1p1/.../digtop_final_route_eco.v
2nd option: do it old way of reading in 1p0 config, 1p0 def and 1p1 directives.
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loadConfig dbs/filler/filler.enc.dat/digtop.conf => load previous config file for VDIO. Change dir path (set cwd) to present dir in this file. Config file only has path locations of digtop.v (note that even though this is verilog file for filler, it doesn't have any filler cells in it, as they don't exist in tech .lib file), tech .lib and tech .lef files. It doesn't have def file info, so we have to do DefIn to read def file.
# Read 1p1 eco_directives => This adds new cells, makes new connections etc to 1p0 verilog file to make new 1p1 file.
source tcl/eco_directive_1p1.tcl
# Or other option is to modify old netlist manually to create new netlist, and read that new netlist.
#set rda_Input(ui_netlist) "/db/.../digtop_final_route_1p1.v" => This overwrites the "i/p netlist" in loadConfig above
#commitConfig => This commits the config file so that all parameters spec above are applied
# ECO DEF in the old DEF file. since new verilog design is in memory and we are reading old def file, tool can figure out new changes for 1p1.
#-useGAcells GACoresite => specifies GA Core site to use for gate array eco. In cell lef file, it looks for cells with "SITE = GACoresite name" specified here. Regular stdcells have "SITE CORESITE", while GA cells have "SITE GACORESITE". That's how tool knows which cells are ECO cells that can be built from filler cells. this cmd implies "postmask" mode.
#-suffix _SPARE_DELETED => Appends the specified suffix to cells that appear in the DEF file but have been deleted in the new netlist. Default: _SPARE
#-postMask => When used with -postmask option, tool can only change nets, not cells. tool checks for cells that exist in memory but not in def, and marks them as unplaced. It then maps these to fillers/spares during ecoPlace. Modified nets which are found in both memory and DEF file, but whose connections are different, are processed during ecoRoute. When -postMask option is not used, it implies pre-mask mode, which can change cells too (it can put any new cell in empty space of fillers).
ecoDefIn -postMask -reportFile ecoDefIn.rpt /db/YELLOWSTONE/design1p0/HDL/FinalFiles/digtop/digtop_final_route.def => Restores physical information from an old design and compares this information with the new design (modified verilog using directives bove). It gives report on screen saying what new inst/net were added, etc (also dumps it in report file ecoDefIn.rpt specified above).
# Specify Spare Gate (-inst specifies instance name and NOT module name) This is needed only if we are not using gate array as spares (i.e. GA cells are not specified above).
specifySpareGate -inst spr_*/*spr_* => use any spare cell in spare modules.
specifySpareGate -inst spare_*/spare_inv_* => if you want to use only inverters
specifySpareGate -inst I_scan_iso_out/g1453 => This specs any extra gate (unused) as a spare cell. This is useful when we have some usuned gates in netlist that we want to use for eco purpose.
After running one of the options above, run ecoPlace and ecoRoute.
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ecoPlace -useSpareCells true
#user intervention to change spare cell mapping. Provide instance name and NOT module name
ecoSwapSpareCell i_inst/eco_inst_an2 spr_3/spr_gate65 => gate "spr3/spr_gate65" from spare cell module is mapped to i_inst/eco_inst_an2. Here eco instance an2 was already mapped to some spare cell, but we didn't like the mapping, so we swap this cell with this other spare cell. Now, spr_gate65 becomes eco_inst_an2, and eco_inst_an2 becomes spr65
# ECO Route new netlist. If only certain metal layers, specify them
ecoRoute -modifyOnlyLayers 1:3
setNanoRouteMode -quiet -drouteFixAntenna true => set this if antenna errors still remain
ecoRoute -modifyOnlyLayers 1:3 => rerun eco route if errors are still there
#ecoRoute may not be able to route because it doesn't touch non-eco nets. Rerun ecoRoute until all errors are fixed. If errors still remain, we can run Nanoroute directly in eco mode. However, ecoRoute is still preferred to be run since it does preprocessing which minimizes routing changes. Cmds below do the same job as ecoRoute above, but can move non-eco nets too.
setNanoRouteMode -quiet -drouteFixAntenna false => optional, improves routing.
setNanoRouteMode -quiet -routeWithEco true
setNanoRouteMode -quiet
#setNanoRouteMode -routeEcoOnlyInLayers 1:3 => can use this single cmd or use these 2 cmds:
setNanoRouteMode -quiet -routeBottomRoutingLayer 1 => bottom routing layer has to be the lowest layer on which there are existing nets. Otherwise error says: "conflict with already existing routed wires on layer x-1"
setNanoRouteMode -quiet -routeTopRoutingLayer 3 => similarly, top routing layer has to be the highest layer on which there are existing nets.
setNaonoRouteMode -quiet routeSelectdNetOnly false
routeDesign -globalDetail => instead of this, we can also use: globalDetailRoute 100.0 1200.0 350.0 600.0 => specify co-ords if you want to reroute within a certain area. Although globalDetailRoute and "routeDesign -globalDetail" seem to be doing the same thing, they result in different results. "routeDesign -globalDetail" gives better results
#NOTE: keep on rerunning "routeDesign -globalDetail" until it passes all drc. (set antenna fix to false)
#Do not use the globalRoute command in ECO mode (use globalDetailRoute as shown above. globalRoute only performs global routing, while detailRoute only performs detailed routing).
#If more than 10 percent of the nets are new or partially routed, run full global and detailed routing instead of ECO routing (set routeWithEco false so that routing is done from scratch. Most of the times, it fixes all routing issues.)
#to route only a list of nets, which are in selectnets.txt file (one net per line)
set NET_FILE [open "selectnets.txt"]
foreach i [ read $NET_FILE ] {
selectNet $i => can only select one net at atime. wildcards are allowed
}
close $NET_FILE
#route these nets
setNanoRouteMode -routeSelectedNetOnly true => routes selected nets only. default is false (routes all nets).
routeDesign -globalDetail
#set_attribute -net <netName> -skip_routing true => to skip routing on selected nets, useful when we don't want to touch nets which are on layers above or below the eco routing layers. Since we can only specify one net_name, we have to use this cmd multiple times for multiple nets. However, this is dangerous to use, as set_attribute ties the attribute with that net, and it is saved with the database. so, next time encounter runs on this database, this attribute is still there, unless we set attribute to false.
# Save design
saveDesign ./dbs/eco_filler_1p1/eco_filler_1p1.enc
checkDesign -noHtml -all -outfile ./dbs/eco_filler_1p1/eco_check_design.rpt => checks design for all issues. Necessary as final_check.tcl later doesn't check for floating nets, etc.
2B. with eco_flow.tcl, we saved the new db into filler.enc. So, we need to run steps beyond filler, to run all checks and get the final netlist.
#Note: we should run timing as extra step since we should make sure design is timing clean, before we run PT.
timeDesign -signoff -reportOnly -prefix digtop_post_route_signoff
timeDesign -signoff -reportOnly -hold -prefix digtop_post_route_signoff
#run post route opt if timing not met or any other violations
setOptMode -effort high
optDesign -postRoute -hold -prefix digtop_post_route_opt
#now run steps beyond filler
source tcl/final_check.tcl => to verify conn, etc.
source tcl/export_final.tcl => run extractRC to generate spef, get final verilog and defout.
3. run Formality to check RTL against ECO netlist. (For ECO netlist, use verilog generated above)
4. Rerun PT to check if timing is ok
5. Rerun all RTL sims and gate sims
6. Regenerate Tetramax patterns and rerun gatesims
7. Import Netlist and DEF to Cadence for top sims and tapeout
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ECO changes using gate array cells (post mask):
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When we use GA cells, we don't have any GA cells in netlist. For doing ECO change, we modify the original netlist to add ECO cells ending in E (made from GA cells) , and then in the layout, appr filler cells are connected to form these GA cells.
These ECO cells have a prefix E at the end to indicate that they are GA cells (i.e IV110E). These cells are generated from base filler cells (FILLER5, FILLER10, etc) which are present in layout. These filler cells were inserted in layout during the filler step (where these base filler cells are filled first and then any remaining spaces are filled with Dcap fillers). Tool figures which E cells can be replaced with which FILLER cells is by looking at physical of cells. NOTE: filler cells are never removed from design. Tool just picks up appr space where ECO cell can be placed, and makes metal connections to reflect the change. Filler cells are still unmodified under the ECO cell.
1. first make sure that ECO filler cells were put in 1p0 design using these 2 cmds:
addFiller -cell FILLER5 FILLER10 FILLER15 FILLER20 FILLER25 FILLER30 FILLER40 FILLER50 FILLER55 -prefix FILLER_ECO
addFiller -cell SPAREFILL1 SPAREFILL2 SPAREFILL4 SPAREMOSCAP3 SPAREMOSCAP4 SPAREMOSCAP8 -prefix FILLER_NORMAL
2. get the i/p netlist from 2p0 and modify it manually to add the new eco cells (ie IV110E, AN210E, etc) that need to be added, connecting them appropriately. name it as dig_top_noPhys_2p1.v
ex: IV120E eco2_2p1_inv27 (.Y(eco2_2p1_prdata_27_bar), .A(eco2_2p1_prdata_27));
3. Once done with changes, read the old layout db and new netlist
ecoDesign -postMask -noEcoRoute -noEcoPlace dbs/handoff_20121106.enc.dat dig_top /data/PROJECT/.../dig_top_noPhys_2p1.v => we don't do eoPlace and ecoRoute as we do it in separate steps
4. do ecoplace using GA cells
ecoPlace -useGAFillerCells "FILLER55 FILLER50 FILLER40 FILLER30 FILLER25 FILLER20 FILLER15 FILLER10 FILLER5" => these filler cells should not have FIXED attribute in def file, else tool would not pick these for replacement, and will try to move around other std cells (which is incorrect).
5. If placement causes any errors (like overlapping placement etc), fix it by deleting and moving
eg: deleteInst FILLER_pdLogic_18457 (delete and then move/add filler cells manually and place them at correct location)
6, do ecoRoute
ecoRoute
7. If ecoRoute doesn't fix all routing violations even after multiple attempts, do full blown routing. Can be done from GUI also: Route->NanoRoute->Route. Unselect ECO ROute and select "Global Route, Detail Route". Check "Fix Antenna". If you want to fix net by net, select "selected nets only" and select on those nets on encounter layout gui.
setNanoRouteMode -quiet -routeWithEco true => may be set to false if we want to do full blown route
setNanoRouteMode -quiet -drouteFixAntenna true
setNanoRouteMode -quiet -routeTopRoutingLayer default
setNanoRouteMode -quiet -routeBottomRoutingLayer default
setNanoRouteMode -quiet -drouteEndIteration default
setNanoRouteMode -quiet -routeWithTimingDriven false
setNanoRouteMode -quiet -routeWithSiDriven false
routeDesign -globalDetail -viaOpt -wireOpt
8. confirm location of newly added cells and then save new db
selectInst *_2p1*
saveDesign ./dbs/handoff_eco_2p1
9. Now run steps 2B and beyond (step 2B, 3-7) as shown in Normal filler cell flow. Run timing, optDesign and then steps beyond filler.
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ECO directives (old way):
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to make new connections, we use the 5 cmds listed below in tcl/eco_directive_1p1.tcl.
NOTE: all cmds specify instance name of any module, and NOT the module name itself. However, if we use -moduleBased, then we specify module_name itself. As module_name is unique for each instance in the synthesized netlist (see final synthesized netlist format desc above), it works OK.
addModulePort: To add port or bussed port to a module. Module should not have net with that name. Ex:
addModulePort i1/i2/i3 p1 input => adds i/p port p1 on instance i3(in hier i1/i2).
attachModulePort: Attaches a port in the specified instance (or top level) to a net. Seems like this cmd attaches ports to nets outside the module (i.e the net has to be at a higher level of hier than the port). This cmd doesn't detach anything, so detachModulePort cmd also needed. (this is different than attachTerm which does detach automatically)
attachModulePort i1/i2/i3 p1 i1/i2/n1 => connects port p1 on i1/i2/i3 to the net i1/i2/n1.
detachModulePort: Detaches the net connected to the specified port on the specified instance.
detachModulePort i1/i2/i3 p1 => detach port p1 from module i1/i2/i3
addNet: Adds a net to the design. The net can be logical or physical. Ex:
addNet i1/n1=> adds net i1/n1
addInst: Adds an instance and places it in the design. Ex:
addInst -cell BUF1 -inst i1/i2 -loc 100 200 => adds buffer instance i1/i2 at location 100, 200. (-cell specifies master of instance while -inst is the actual instance)
attachTerm: Attaches a terminal to a net. If the terminal already connects to a different net, the software first detaches the terminal from the current net, then attaches it to the new net. Previously we used to use: detachTerm to detach the existing net, but not needed any more. Ex:
attachTerm i1/i2/i3 in1 i1/i2/net26 => attaches terminal in1 of instance i1/i2/i3 (in1 is a port of i3) to net i1/i2/net26
NOTE: addModulePort and attachModulePort cmd can be avoided by using attachTerm which is more generic cmd.
#For ex, to connect internal gate o/p within one module to internal gate i/p within another module, use this:
attachTerm spi_regs/eco2_inv A clock_reset_gen/n37 => attaches terminal A of inv in "spi_regs" module to net n37 in "clock_reset_gen" module. Note, this cmd first figures out the port thru which pin A of inv can be accessed, and then connects the net to that port. So, if there are multiple connections to that port, all of them will get conncted. In essence, this cmd connects a port to a net. If the port doesn't exist, it creates a port in the module (spi_regs) with that netname (n37).
#alternative way would be to have ports and then connect them
addModulePort spi_regs eco2_spi_inp input
addNet -moduleBased digtop eco2_rst_connect
attachModulePort spi_regs eco2_spi_inp eco2_rst_connect => created port for "spi_regs" module and connected net to it.
addModulePort clock_reset_gen eco2_clk_reset_out output
attachModulePort clock_reset_gen eco2_clk_reset_out eco2_rst_connect => created port for "clock_reset_gen" and connected same net to it.
attachModulePort clock_reset_gen eco2_clk_reset_out clock_reset_gen/n37 => connects the other end of port to net n37
Steps: to do ECO fix, first find the net name to where u want to insert ur logic. Use debussy on gate verilog and find the net on schematic of that module. If o/p net of new logic goes to fewer instances compared to i/p net of new logic, leave i/p net as existing net name and make o/p net as new net. Do vice versa (i.e if o/p goes to more instances, leave o/p net as existing net and make i/p net as new net)
Ex: attach an inverter to input of flop
#-moduleBased <module_defn_name> sets the module defn_name so that hier is not required. Note we specify module_defn_name and NOT module_instance_name. As module_name is unique for each instance in the synthesized netlist (see final synthesized netlist format desc above), it works OK.
addInst -moduleBased spi_regs_test_1 -cell IV140 -inst eco1_inv_before => add inx instance
addNet -moduleBased spi_regs_test_1 eco1_reg_input => add new net to connect to o/p of inx
attachTerm -moduleBased spi_regs_test_1 eco1_inv_before A n610 => attach inx i/p to existing net n610 (we chose i/p since n610 might be driving multiple loads)
attachTerm -moduleBased spi_regs_test_1 eco1_inv_before Y eco1_reg_input => attach inx o/p to new net.
attachTerm -moduleBased spi_regs_test_1 vbg2_op_out_reg_2 D eco1_reg_input => attach FF D i/p to new net. This causes exising net n610 to disconnect from D i/p of FF. If n610 wasn't connected to any other o/p, it would become floating.
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conformal ECO:
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Here, conformal generates the patch that can be used in VDIO. Run LEC:
lec -12.10-s400 -gui -xl -ecogxl -log ./logs/eco.log -dofile scripts/eco.do => -ecogxl enables post mask eco.
eco.do file:
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1. set common settings:
set log file eco.log -replace
usage -auto
2. Read library: (note that .liberty files are read, and NOT verilog models)
read library -both -liberty /db/pdkoa/.../MSL270_N_27_3_CORE.lib
read library -both -liberty /db/pdkoa/.../MSL270_N_27_3_CTS.lib -append
3. Read design. Read 1p0 final PnR netlist as golden and new synthesized netlist as revised.
#NOTE: spare cell modules are missing from revised netlist since they are added in PnR flow
read design -verilog -golden -sensitive -root digtop /db/HAMMER_OA/design1p0/HDL/FinalFiles/digtop/digtop_final_route.v
read design -verilog -revised -sensitive -root digtop /db/HAMMER_OA/design1p1/HDL/Syhnthesis/digtop/netlist/digtop_scan.v
4. set eco directives:
A. enable ECO meodeling directive. It's necessary to have this for eco. Other directives are optional.
1. set flatten model -eco => prevent default flatten modeling from removing important info that is vital to correlate the ECO change back to original netlist. It's a macro that enables a number of related modeling options such as "set flatten model -keep_ignored_po -noremove_real_buffer" etc.
2. set flatten model -enable_analyze_hier_compare => analyze hier bdry (module bdry) comp of flattened design. Needed to do hier comparison later.
B. other directives:
set flatten model -Latch_fold => if needed
set flatten model -seq_constant => if needed
set flatten model -gated_clock => if needed Gated clock control
#scan shift en turned off since scan chain may be different in new synthesized netlist. scan_mode still allowed both 0/1 values as scan_mode signal is just like any other logic signal.
add pin constraints 0 scan_en_in -golden =>
add pin constraints 0 scan_en_in -revised =>
#specify any new pins added/deleted at top level
#ex: new pin new_in2 added at top level digtop which also goes into submodule ctrl. so, we add this eco pin in both modules for golden (since they don't exist in golden. If we don't specify ports for modules/sub-modules, then tool is not able to add it for golden, and so reports them as unmapped points.). -input specifies i/p pin, while -output specifies output pin (default is input).
NOTE: We specify module definition name and NOT instance of module, as pin needs to be added on module defn.
add eco pin scan_out_iso new_in2 -input -golden => use delete eco pin for deleting pins.
add eco pin scan_out_iso new_out2 -output -golden => scan_out_iso is a submodule but still referenced as module since conformal flattens the design.
add eco pin clock_reset_gen_test_1 new_out2 -output -revised => clock_reset_gen_test_1 is the module defn name in revised netlist.
set mapping method -unreach
5. analyze hier bdry and do hier comaparison (lec mode). It should show non-eq points. Then create patch based on that.
set system mode lec
#while doing hier comp, hier_analyze.do file is generated which has all cmds for hier comparison. ecopins.do file is also generated which has eco cmd for adding pins to modules which need it in new netlist
analyze hier_compare -dofile hier_analyze.do -replace -constraints -verbose \
-threshold 0 -noexact_pin_match -noexact_module_match \
-eco_aware -input_output_pin_equivalence -function_pin_mapping -ecopin ecopins.do
add compared points -all
compare => should show non eq points
report statistics => reports
compare eco hierarchy => we break down comparison to sub-module level
report eco hierarchy -noneq -verbose
analyze eco -hierarchical patch.v -replace -ecopin_dofile ecopins.do -preserve_clock => creates a patch file which has only the gate changes needed for 1p1
6. apply patch, then optimize patch based on spare/GA cells, then write final netlist.
set system mode setup
dofile ecopins.do => add pins needed to modules.
#apply patch: -auto Automatically reads in and applies all patches that were created with the ANALYZE ECO cmd in the current session. (-keephierarchy specifies that the ECO changes will be put in a sub-module. Do not use this option, as that will cause problems in VDIO)
apply patch -auto => shows patch file being read and applied.
#### this section optional = to check if patch is good
set system mode lec
add compare point -all
#delete compare point A_REG[0] => To omit certain non-equiv points from eco analysis
compare // this checks if patch if good before optimization, design should be equiv (1p0 vs patch)
write eco design -replace -newfile digtop_tmp_eco.v => IF we write out netlist, it will have separate eco modules which will have the new instances/connections. Later, after doing optimize patch, we get netlist which has no separate eco mdules, but the changes are within the existing modules. The netlist with no separate eco modules is the one that can be used in VDIO, else it will give an error for having extra modules.
NOTE: we could stop here and use the netlist generated above in VDIO. However, there are 2 problems. First, the netlist has extra modules, and secondly it has cells in eco_modules which may not be present in spare_cell module, so these will need to be substituted by cells which are actually present in spare_cell module. So, optimize patch step needed.
####
set system mode setup
###spare/GA cells added for Post-mask eco only. For pre-mask, ignore this section
add spare cell -freedcell => add any freed up cells to be used as spare cells
add spare cell -deffile /db/HAMMER_OA/design1p0/HDL/FinalFiles/digtop/digtop_final_route.def -sparecell spr_*/spr* => this adds all spare cells to be used for eco
#add spare cell -deffile /db/HAMMER_OA/design1p0/HDL/FinalFiles/digtop/digtop_final_route.def -sparecell GAFILL* => this adds all GA cells for eco
#delete spare cell -sparecell spr_*/spr_AN2* => This disables any specific spare cell that we don't want to use
report spare cell => This shows all avilable freed cells as well as spare cells
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#optimize patch does the actual mapping to get new netlist generated
optimize patch -verbose -usespare -workdir WORK \ => for postmask using spare/GA cells, use -usespare
-library "/db/pdkoa/.../MSL270_N_27_3_CORE.lib \
/db/pdkoa/.../MSL270_N_27_3_CTS.lib" \
-netnaming eco_net_%d \ => within each module, new eco nets named as eco_net_1, eco_net_2, etc
-instancenaming eco_instance_%d \ => within each module, new eco instances named as eco_instance_1, eco_instance_2, etc
-rcexec "rc -12.20-s014" \ => version of rc to use
-sdc /db/HAMMER_OA/design1p1/HDL/DesignCompiler/digtop/sdc/hmr_constraints.sdc \
-def /db/HAMMER_OA/design1p0/HDL/FinalFiles/digtop/digtop_final_route.def \
-lef /db/pdkoa/.../vdio/lef/msl270_lbc7_tech_3layer.lef \
/db/pdkoa/.../vdio/lef/msl270_lbc7_core_iso_2pin.lef \
-mapscript mapping.tcl => This is optional and creates a mapping file which maps new eco cells with location aware spare/GA cells. this can be used in PnR, so that PnR doesn't have to do tedius process of mapping
#report eco changes -script -file test.script -replace => generates ECO inst set file that can be used directly in verplex(by using -script option) or EDI (by using -encounter option. it generates eco directive file)
report eco changes > eco_changes.rpt => reports eco chamges for each module (as new nets,instances,pins,etc)
write eco design -replace -newfile digtop_final_route_eco.v => new netlist can be tkdiff with old netlist to see differences.
exit
7. Now use the netlist generated above in Encounter to do place and route as in any eco flow. This new netlist above just has new instances added/deleted, but doesn't have the mapped spare cell isntance connection. This will be done in EDI. However, we will still need to modify the above netlist to add scan chain connection for any newly added flops.
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DIFF the layout: After the ECO change, verify the differences to make sure, only desired metal layers got changed.
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A. generate laff files for digital design for both 1p0 db and 1p1 db.
1. On cadence CIW (cmd/log window, NOT the lib mgr), goto TI_Utils->Translators->Physical->LAFF_out@TI. We get new pop up box (CDS2Laff).
2. Provide Form Template File name if you have any(.cds2laff.ctrl). This file has all the info in it, so that we don't need to type anything in boxes below. you need to load this file to save typing. .cds2laff.ctrl lools like this (resides in /proj/DRV9401/users/kagrawal/DRV9401 or anywhere else):
topcells
Hawkeye_digtop_1p1 digtop layout
end
laffname /sim/BENDER/pindi/assura/digtop_1p1.laff
nosystemlayers
layermap /data/pdk/lbc8/rev1/cdk446/4.6.a.19/doc/cds2laff.map
logfile /data/BENDER/users/pindi/BENDER/CDS2LAFF.LOG
signal label
If .cds2laff_1p1.ctrl file is not loaded, then run steps 3 to 7, and then save this template as .cds2laff.ctrl.
3. leave run dir as current (.).
4. choose cell type as "cellname" and Provide Library name (Hawkeye_digtop_1p1), cell name(digtop), view name (layout)
5. Provide Laff file name to write to (ex: digtop_1p1.laff).
6. choose layer map table => this comes from the pdk doc dir. Without this layer mappings will not be correct and we may get a "syntax error" on running difflay (for HPA07, it's /data/pdkoa/50hpa07/2012.11.13/cdk/itdb/doc/cds2laff.map)
6. choose signal type as "label". (leave "exclusive layer mapping" as ticked)
7. click "OK", and the digtop_1p1.laff file is generated in the dir mentioned. (choose yes and no for the first 2 options that pop up)
Repeat steps 1 thru 7 for digtop_1p0 design to generate digtop_1p0.laff (by changing .cds2laff_1p0.ctrl file appr)
NOTE: Look at CDS2LAFF.LOG file. At the very bottom, we should see 0 errors and 0 warnings.
B. Diff b/w digtop_1p0.laff and digtop_1p1.laff
Open difflayman tool (by typing difflayman on the unix command window). On the gui, provide the laff path for the 1p0 and 1p1 laff files, cell names as digtop, path to summary out file and log path file, and then click submit. A new window pops up. when it's done, then you can click on "view summary" to see what layers changed.
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