synthesis: Cadence RC
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- Last Updated: Sunday, 21 June 2020 06:04
- Published: Wednesday, 26 September 2018 05:26
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For running synthesis in Cadence RC (RTL Compiler):
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RC does global opt which isolates timing critical and non-timing critical paths before mapping them to gates. This results in better design than tools which do local/incremental opt in which design is mapped to gates first and then timing is opt.
RC:
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Create a dir: /db/NOZOMI_NEXT_OA/design1p0/HDL/RCompiler/digtop/
NOTE: everything in RC is stored in virtual dir starting at / . So, we see / after many of the cmd which specifies that the cmd applies to all of the design (/ implies the top level dir of design. It's NOT for continuation on next line)
cp .synth_init file from some other dir. It is similar to .synopsys_dc.setup and has search paths, lib path and other variables setup. RC searches for this file first in installation dir as master.synth_init file, then in home dir for .cadence/.synth_init file, and finally in current dir for .synth_init file. It has the following and many more settings:
#set_attribute <attr_name> <attr_value> <object> => sets value of an attribute. In RC, there are predefined attr associated with objects. We can set only those attr on objects, which are read-write. Also, some attr can only be set at root (/) level, while some can be set on "designs" objects only.
ex: set_attribute lp_clock_gating_exclude true /designs/digtop => setting attr on designs/digtop object
#we can also create our own attribute:
set_user_attribute <attr_name> <attr_value> <object>
#get_attribute <attr_name> <object> => gets attr value on single object only.
ex: get_attr load /libraries/slow/inx1/A
#set library paths to max delay lib. When we set this attr, RC scans these .lib files and reports errors/warnings in these files such as usupported constructs, etc. It also reports unusable cells (marked as "dont_use" in these lib files. usually all CTS cells and dly cells are marked as dont_use). Then it sets attribute of root "/": library = PML30_W_150_1.65_CORE.lib PML30_W_150_1.65_CTS.lib
set_attribute lib_search_path {/db/pdkoa/lbc8/2011.06.26/diglib/pml30/synopsys/src} /
set_attribute library {"PML30_W_150_1.65_CORE.lib" "PML30_W_150_1.65_CTS.lib"} / => max library. library attr is a root attr and so it's applied at root dir. This cmd populates the /libraries virtual dir.
#WLM, PLE, spatial or Physical RC can be used for wire modeling. WLM is worst and Physical is best. WLM is default.
#RC-WLM: info in .lib file. has WLM models. look in liberty.txt for details. WLM provides same res/cap for all layers (which is Res=0, cap=1pf/unit_length). In reality, res=0.2ohm/um and cap=0.2ff/um for LBC7 process. so, WLM is overly optimistic for net delays, and effectively treats net delays as 0.
set attr interconnect_mode wireload /
set attr wireload_mode top /
#RC-PLE (physical layout estimation), RC-spatial, RC-physical(RCP): needs tech_lef and std_cell_lef files in addition to .lib files. cap_table and floorplan def files are optional for PLE and spatial, but floorplan .def file is required for physical as it has pin location, macro placement, etc. PLE does good job modeling local interconnects since physical cell size as well as various metal layer info is present. Providing cap table info gives better estimate of cap/res as actual cap/res taken for each layer. spatial models longer wires better, as it does coarse placement under the hood. providing floorplan def helps a lot in RC-spatial.
set attr interconnect_mode ple / => not needed as specifying lef files applies PLE.
#when setting attr for lef lib, RC scans these files and reports number of routing layers, number of logic/seq cells, and any warnings/errors etc. It alos looks for consistency b/w tech lef and cap table for width of layers, etc. Then it sets attr "lef_library", "cap_table" for root "/" to named files below.
set_attribute lef_library {"/db/pdk/lbc7/rev1/diglib/msl270/r3.0.0/vdio/lef/msl270_lbc7_core_iso_2pin.lef" "/db/pdk/lbc7/rev1/diglib/msl270/r3.0.0/vdio/lef/msl270_lbc7_tech_3layer.lef" } / => both tech and std cell lef files provided. stored in compiler memory at /libraries
set_attribute cap_table_file {/db/pdk/lbc7/rev1/diglib/msl270/r3.0.0/vdio/captabl/3lm_maxC_maxvia.capTbl} / => helpful. This shows res and cap for various width and spacing for each layer and vias.
For running spatial or physical, include it in "synthesize" cmd as follows when running rc:
synthesize -to_mapped -spatial -effort [low|medium|high] => spatial
synthesize -to_placed => physical. It runs First encounter (FE) placeDesign, trialroute, extractRC, buffers long wires, brings in physical timing and performs inc opt. Then we can do: write_encounter digtop. We can output a def file which is fully placed legal design pre-CTS. We can then start from the CTS step in FE.
##Default undriven/unconnected setting is 'none'. These connect each i/p, o/p or internal undriven signal (wire/reg) to specified value. none implies undriven signal remains undriven. post elaboration netlist will have appr gates and assign stmt to support driven value.
#set_attribute hdl_unconnected_input_port_value 0 | 1 | x | none /
#set_attribute hdl_undriven_output_port_value 0 | 1 | x | none /
#set_attribute hdl_undriven_signal_value 0 | 1 | x | none /
#naming style in verilog netlist generated. %s is variable name, %d is individual bit
set_attribute hdl_array_naming_style %s_%d /
set_attribute bus_naming_style %s_%d /
#Selects the Verilog style for unconnected instance pins. default is to write out dummy wires for unconnected instance pins. ex: for this line in original RTL: DELAY1 DL (.A(A2)); //DL module has 1 i/p port and 1 o/p port which is not coded in RTL.
#full => Put UNCONNECTED for nets connecting unconnected instance pins in gate netlist. ex: DELAY1 DL(.A (A2), .Z (UNCONNECTED));
#partial => Put the unconnected instance pins in gate netlist, but no wire to connect to it. ex: DELAY1 DL(.A (A2), .Z ());
#none => do nothing. ex: DELAY1 DL (.A(A2));
set_attribute write_vlog_unconnected_port_style partial / => remove UNCONNECTED nets from pins.
#set_attribute tns_opto true / => turn ON TNS
##set_attribute wireload_mode <value> /
set_attribute information_level 7 /
set_attribute hdl_track_filename_row_col true / => To include the RTL file name and line number at which the DFT violation occurred in the messages produced by check_dft_rules
#clk gating set for 3 or more flops
set_attribute lp_insert_clock_gating true /
set_attribute lp_clock_gating_min_flops 3 /
set_attribute lp_clock_gating_prefix CLK_GATE /
#do not merge equiv flops and latches
set_attribute optimize_merge_flops false /
set_attribute optimize_merge_latches false /
#optimize const flops. By default, set to true so that const 0/1 can be propagated thru flops, thus allowing removal of flops.
#set_attr optimize_constant_0_flops false
#set_attr optimize_constant_1_flops false
#use_tiehilo_for_const: const are tied to hi/lo cells. This doesn't connect all 1'b1/1'b0 to tiehi/lo cells , so we use another cmd after synthesize to fix remaining 1'b1/1'b0 problem. options:
#duplicate => Allows each constant assignment to be replaced with a tie cell.
#unique => Allows only one unique tie cell in the netlist. Treatment of the remaining constant assignments depends on settings of the remove_assigns and set_remove_assign_options
#none => Prevents the replacement of constants in the netlist with tie cells
set_attr use_tiehilo_for_const unique => only 1 unique tie cell should be added.
vaious other attr can be set in .synth_init file, before running rc cmds.
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run RC: script run_rc
rc -10.1-s202 -over -f ./tcl/top.tcl -logfile ./logs/top.log -cmdfile ./logs/top.cmd
#IMP: for getting help with cmds on rc,
rc:/> cdnshelp => brings up cdns help browser for that rev of tool
rc:/> man or help <cmd_name>. Tab key shows all possible completions.
rc:/> man lib_serach_path => this will show man page for attr "lib_serach_path"
# write_template => template script can be generated by running write_template with various options
write_template -outfile run.tcl -full => creates script with all basic cmd, dft, power, retiming. -simple creates a simple script.
#running scripts within RC: do a source or include with script file name.
top.tcl:
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#initial setup: (it has set SCAN_EXISTS 0 => choose b/w scan vs non-scan design)
#include/source other files
include tcl/setup.tcl => set varaibles as DESIGN, SYN_EFF, lib path, dir, etc. All lib path, cap_table etc are put in .synth_init file, but can also be put here.
#source tcl/setup.tcl => we can also use source to include the file
#source tcl/analyze.tcl
#read verilog/vhdl/systemVerilog files, elaborate, check design, uniqify and then check for uniquufy
#read_hdl <-v1995 | -v2001 | -sv | -vhdl> [list "$RTL_DIR/global.v" ... " " ] => default lang attr is one specified by hdl_language attribute. The default value for the hdl_language attribute is -v1995. For -vhdl, hdl_vhdl_read_version root attribute apecifies vhdl version, by default it's set to VHDL-1993.
read_hdl -v2001 [list "$RTL_DIR/global.v" ... "$RTL_DIR/digtop.v" ]
#read_netlist design_struct.v => to read gate level netlist
elaborate $DIG_TOP_LEVEL => $DIG_TOP_LEVEL is set to digtop above. This elaborates top level design and all its references. We only specify the top level. It builds data structures, infers registers,performs HDL opt, identifies clk gating and operand isolation candidates.
check_design -unresolved => checks for design problems as unresolved references. Using -all checks for undriven/multidriven ports/pins, unloaded ports/pins, constant connected ports/pins and any assign stmt.
#uniquify not needed as design is uniquified by default.
/*
uniquify $DIG_TOP_LEVEL
#task to make sure design is uniquified
proc is_design_uniquified {} {
foreach subd [find /des*/* -subdesign *] { => look in designs dir for all sub designs
if {[llength [get_attr instance $subd]] > 1 } {
puts "ERROR: design is NOT uniquified"
return
} else { return "design is uniquified" }
}
}
is_design_uniquified => calling the actual procedure
*/
#provide constraints in SDC: 2 options: read sdc file directly by using read_sdc or enter constraints as in DC. eg.
#option 1: read_sdc ./tcl/env_constraints.tcl => reads all DC sdc cmds directly without any prefixing. Useful as same file can be used in EDI/Dc, etc. IMP: we've to add ./tcl and not tcl/, since virtual dir structure is assumed for RC, so it looks for tcl dir in virtual dir, which is not there, so it complains. By changing it to ./tcl, it looks in unix tcl dir in current dir
#option 2: replace all dc cmds with dc::, or change them to RC equiv cmd. ex: dc::set_load ..... We can read these cmds anytime within RC shell or put it in file and source it: source tcl/env_constraints.tcl. However, same file can't be used in synopsys tools as "dc::" is not sdc cmd.
#env constraints: (see in sdc.txt for cmd details: some cmds in DC sdc file aren't std sdc cmd, so they have to be replaced with appr RC cmds).
option 1: read_sdc ./tcl/env_constraints.tcl => same file can be used in EDI
option 2: prepend sdc cmds with dc::.
env_constraints.tcl file: op_cond (PVT), load (both i/p and o/p), drive (only on i/p), fanout(only on o/p) and WLM. Of these, op_cond and WLM are already specified in .synth_init file. dont_touch, dont_use directives also provided here.
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#i/p driver: use "set_driving_cell" as it's std sdc cmd
#set_attribute external_driver [find [find "MSL270_W_125_2.5_CORE.db" -libcell IV110] -libpin Y] [all_inputs] => DC cmd
set_driving_cell -lib_cell IV110 [all_inputs] => sdc cmd. use this for both RC/DC
#o/p load: use "set_load" as it's std sdc cmd. However, to automatically use i/p cap for IV110 as load cap for o/p ports, we need to use diff cmd in DC vs RC. Then we can use set_load.
if {$RUN_PNR ==1} {
set output_load 0.005
} else {
#set output_load [get_attribute capacitance "MSL270_W_125_2.5_CORE.db/IV110/A"] => get_attribute is native cmd for both RC/DC with different syntax, so it gives an error in RC. Also, it can't be used in EDI. For RC, we use "get_liberty_attribute" which is simpler.
set output_load [get_liberty_attribute capacitance [find [find "MSL270_W_125_2.5_CORE.db" -libcell IV110] -libpin A]] => get_liberty_attribute isn't supported in EDI. use this in RC only.
#set output_load [get_attribute max_capacitance [find [find / -libcell MSL270_W_125_2.5_CORE/IV110] -libpin A]] => here get_attribute is used and full path of libcell is provided since we start search from top level virtual dir "/".
}
set output_load_4x [expr 4 * $output_load]
set_load -pin_load $output_load_4x [all_outputs]
write_set_load > ${_OUTPUTS_PATH}/net_cap.txt => shows load values for all the nets in design in set_load format. since set_load is sdc cmd, values are shown in pf. Run this in RC to make sure units are correctly shown.
#set_dont_use
read_sdc ./tcl/dont_use.tcl
#set_dont_touch
read_sdc ./tcl/dont_touch.tcl
#write out HDL in cadence primitives, before doing synthesis
write_hdl > ./netlist/${DESIGN}.PreSyn.v
#initial synthesis
synthesize -to_generic -eff low -no_incr => opt mux and datapath and stops before mapping. It contains tech independent components. It does const propagation, resource sharing, logic speculation, mux opt, CSA (carry save adder) opt. -no_incr allows it to opt logic from scratch.
synthesize -to_mapped -eff low -no_incr => maps design to cells in tech lib and optimizes it. It evaluates every cell in design and resizes to improve area and power. If -incr option is used, then it runs DRC, timing, area cleanup and critical region resynthesis to meet timing. -incr preserves current impl and performs opt only if there is an improvement in overall cost of design. -to_mapped is default option.
#when we synthesize with map, we see "global mapping target info" on screen and in log file. In each cost group, RC will estimate a target slack number based on the design structure, libraries, and design constraints. This slack number is the estimated slack on the worst path of a cost group seen before mapping. During mapping, RC will try to structure logic, and select cells to bring this target slack number close to 0.
#puts "Runtime & Memory after initial synthesize"
#timestat MAPPED
generate_reports -outdir $_REPORTS_PATH -tag ${DESIGN}.initial => reports area, gate, timing in separate files.
#report area > $_REPORTS_PATH/${DESIGN}.initial_area.rpt => no need of this cmd, as area already reported by above cmd
write_hdl > ${_NETLIST_PATH}/${DESIGN}_initial.v
#### design constraints => case_analysis, i/p,o/p delays, clocks/generated clocks, false/multicycle paths
if {$SCAN_EXISTS} {
read_sdc ./tcl/case_analysis.tcl => set_case_analysis only if scan exists to force part in functional mode. We want to have simple functional timing paths, and not have paths for scan_mode too. strictly speaking, this stmt is not required.
#case_analysis.tcl
#set_case_analysis 0 scan_mode_in => force scan_mode to 0 so that we see timimg paths b/w diff clocks. We are not interested in timing when part is in scan mode.
}
read_sdc ./tcl/constraints.tcl => has i/p, o/p delays
#constraints.tcl
set_input_delay 0.2 -clock clk1 [all_inputs]
set_output_delay 0.4 -clock clk1 [all_outputs]
}
#clocks (set_drive and create_clock/create_generated_clock for all clks).
read_sdc ./tcl/clocks.tcl
#we don't set uncertainty in clocks.tcl, since we use that file in EDI, where we want to use real clk delays)
set_clock_uncertainty $SPI_SCK_skew SPI_SCK
#turn off clk gating if not wanted (in .synth_init we set clk gating to true)
set_attribute lp_insert_clock_gating false /
#read false_paths/multi-cycle paths
read_sdc ./tcl/false_paths.tcl
read_sdc ./tcl/multicycle_paths.tcl
#to prevent any logic changes on instances of specified cells.
#map_size_ok => Allows resizing, unmapping, and remapping of a mapped sequential inst during opt, but not renaming or deleting it.
#size_ok => Allows resizing a mapped inst during opt, but not deleting, renaming, or remapping it.
set_attr preserve map_size_ok [find I_S1_CONTROL -instance instances_seq/sm_reg*]
#set_attr preserve true => Prevents logic changes to any object in the design during opt. needed
# Incremental Compile with high effort
source tcl/compile.tcl
###compile.tcl has following cmds.
#report worst case timing by setting this variable:
set_attribute map_timing true /
## Define cost groups (clock-clock, clock-output, input-clock, input-output)
if {[llength [all::all_seqs]] > 0} {
define_cost_group -name I2C -design $DESIGN
define_cost_group -name C2O -design $DESIGN
define_cost_group -name C2C -design $DESIGN
path_group -from [all::all_seqs] -to [all::all_seqs] -group C2C -name C2C
path_group -from [all::all_seqs] -to [all::all_outs] -group C2O -name C2O
path_group -from [all::all_inps] -to [all::all_seqs] -group I2C -name I2C
}
define_cost_group -name I2O -design $DESIGN
path_group -from [all::all_inps] -to [all::all_outs] -group I2O -name I2O
#report all failed cmds when reading sdc
echo "failed sdc cmds" > $_REPORTS_PATH/${DESIGN}.after_constrain.rpt
echo $::dc::sdc_failed_commands >> $_REPORTS_PATH/${DESIGN}.after_constrain.rpt
echo "The number of exceptions is [llength [find /designs/$DESIGN -exception *]]" >> $_REPORTS_PATH/${DESIGN}.after_constrain.rpt
report timing -lint -verbose >> $_REPORTS_PATH/${DESIGN}.after_constrain.rpt => reports possible timing problems in the design, such as ports that have no external delays (unclocked primary I/O), unclocked flops, multiple clocks propagating to the same clock pin, timing exceptions that cannot be satisfied, timing exceptions overwriting other timing exceptions, constraints that may have no impact on the design, and so on.
#incremental synthesis
synthesize -to_mapped -eff high -incr
#IMP: we might have 1'b0 and 1'b1 in logic at this time. To connect them to tiehi/tielo cells, run this:
insert_tiehilo -all -hilo TO020L -verbose [find -design *] => for both hi/lo connections, same cell used. verbose shows info on screen, as to which 1'b1/1'b0 are still not tied. -all does it for all including scan cells. If we put "-hi TO020 -lo TO020", then tool connects hi connections to one instance of TO020 (to HI pin. LO pin is left floating) and lo connections to another instance of TO020 (to LO pin. HI pin is left floating). So, this results in 2 copies of TO020 cells. By using "-hilo TO020", we use same instance for hi and lo connections.
#reports
generate_reports -outdir $_REPORTS_PATH -tag ${DESIGN}.incremental
summary_table -outdir $_REPORTS_PATH
report timing -num_paths 500 >> $_REPORTS_PATH/${DESIGN}.all_timing.rpt
foreach cg [find / -cost_group -null_ok *] {
report timing -cost_group [list $cg] -num_paths 100 > $_REPORTS_PATH/${DESIGN}.[basename $cg]_timing.rpt
}
report area > $_REPORTS_PATH/${DESIGN}.compile.rpt
report design_rules >> $_REPORTS_PATH/${DESIGN}.compile.rpt
report summary >> $_REPORTS_PATH/${DESIGN}.compile.rpt => reports area, timing and design rules.
#optional reports
report messages >> $_REPORTS_PATH/${DESIGN}.compile.rpt => reports summary of error msg
report qor >> $_REPORTS_PATH/${DESIGN}.compile.rpt
report gates -power >> $_REPORTS_PATH/${DESIGN}.compile.rpt => reports libcells used, total area and instance count
report clock_gating >> $_REPORTS_PATH/${DESIGN}.compile.rpt
report power -depth 0 >> $_REPORTS_PATH/${DESIGN}.compile.rpt
report datapath >> $_REPORTS_PATH/${DESIGN}.compile.rpt => datapath resource report
#write results
write_design -basename ${_OUTPUTS_PATH}/${DESIGN}
write_script > ${_OUTPUTS_PATH}/${DESIGN}.script
write_hdl > ${_NETLIST_PATH}/${DESIGN}.v => final non-scan netlist
####### Insert Scan
if {$SCAN_EXISTS} { => see synthesis_DC.txt for details on this
set_ideal_network [get_ports scan_en_in]
set_false_path -from scan_en_in
source tcl/insert_dft.tcl
}
#insert_dft.tcl has following
source ./tcl/scan_constraints.tcl
#scan_constraints has following:
set_attribute dft_dont_scan true [ list Idigcore/IResetGen/nReset_meta1_reg \
Idigcore/IResetGen/nReset_meta2_reg ]
set_attr dft_scan_style muxed_scan / => mux_scan style
set_attribute dft_prefix DFT_ / => prefix dft with DFT_
# For VDIO customers, it is recommended to set the value of the next two attributes to false.
set_attribute dft_identify_top_level_test_clocks false /
set_attribute dft_identify_test_signals false /
set_attribute dft_identify_internal_test_clocks false /
set_attribute use_scan_seqs_for_non_dft false /
set_attribute dft_scan_map_mode tdrc_pass "/designs/$DESIGN"
set_attribute dft_connect_shift_enable_during_mapping tie_off "/designs/$DESIGN"
set_attribute dft_connect_scan_data_pins_during_mapping loopback "/designs/$DESIGN"
set_attribute dft_scan_output_preference auto "/designs/$DESIGN"
set_attribute dft_lockup_element_type preferred_level_sensitive "/designs/$DESIGN"
#set_attribute dft_mix_clock_edges_in_scan_chains true "/designs/$DESIGN"
---
### define clocks, async set/reset, SDI, SDO, SCAN_EN and SCAN_MODE.
##all dft cmds have these common options:
#define_dft <test_mode | test_clock | shift_enable | scan_chain> -name <testObject> <port or pin name> -create_port -hookup_pin <pin_name> -hookup_polarity <inverted|non_inverted> -shared_in -shared_out
#<port or pin name>: we provide the driving port_or_pin_name. However, that will work only if we code the RTL in a way where the top level port can directly be used as SE, SCLK, SDI, SDO. In many cases, functional pins are used as scan pins by multiplexing them, so if we directly use the port name, that will be incorrect. For ex spi_cs_n being used as scan_shift_en (during scan_mode) has spi_cs_n anded with scan_mode to generate scan_shift_en which is then connected to SE pin of all flops. In this case, internal scan_shift_en needs to be used for SE, so we add option "-hookup_pin B/scan_shift_en_int" so that tool connects this pin to SE of all flops. When you specify this option, the RC-DFT engine does not validate the controllability of any logic between the top-level test-mode signal and its designated hookup pin under test-mode setup (i.e if the hookup pin can be changed to desired value by toggling i/p port or not). The way RTL is coded in our group is we get the pin driven out and then driven back in as dedicated pin for scan purpose (for ex scan_enable_out and scan_enable_in pins). Then we don't need -hookup_pin option. Look in DFT compiler notes (pg 1 back).
#-shared_in is used to indicate that i/p port is used for functional port also. similarly -shared_out is used to indicate that o/p port is used for functional port also. By default, the signal applied to the specified driving pin or port is considered to be a dedicated test signal. By specifying these, we ensure that these test signals will not get constrained in the write_do_lec dofile. Not specifying this option for a shared test signal will result in overconstraining the write_do_lec dofile (by forcing that input port to inactive state) which can lead to false EQs.
#-no_ideal marks the test signal as non-ideal which allows buffering in RC. By default, it's treated as ideal.
----
#force pins for test mode: i.e async set/reset need to be in inactive state, while SCAN_MODE needs to be high.
#define_dft test_mode -name <testModeObject> -active <high|low> -no_ideal -scan_shift <port_or_pin_name> [-create_port] [-shared_in] -hookup_pin <pin_name> -hookup_polarity <inverted|non_inverted>
define_dft test_mode -name scan_mode -active high scan_mode_in
#define_dft test_mode -name scan_reset -active high n_reset => we don't define async set/reset as we force them to 0, when scan_mode=1 (in RTL itself). If we need to toggle n_reset during scan test to have more coverage, then we need to use -scan_shift option which holds the scan signal to its test-mode active value during the scan shift operation of the tester cycle, but is otherwise allowed to pulse during capture cycle (test signal will be treated as a non-scan clock signal by the ATPG tool). -scan_shift option is also needed to generate correct lec.do file, else n_reset pin will get get constrained which will lead to false EQs.
#now define scan_clk, scan_shift_en, scan_data_in and scan_data_out for each chain. Note that these scan_pins are multiplexed with normal functional pins, so -hoopup_pin option is used.
#define_dft test_clock -name <testClockObject> -domain <testClockDomain> -period <delay in pico sec, default 50000> -rise <integer> -fall <integer> <portOrpin> -hookup_pin <pin_name> -controllable => Defines a test clock and associates a test clock waveform with the clock. If you do not define test clocks, the DFT rule checker automatically analyzes the test clocks and creates these objects with a default waveform. -hookup_pin specifies the core-side hookup pin to be used for the top-level test clock during DFT synthesis.
#-controllable => when specifying an internal pin for a test clock, this option indicates that the internal clock pin is controllable in test mode (for example, Built-in-Self-Test (BIST)). If you do not specify this option, the rule checker must be able to trace back from the internal pin to a controllable top-level clock pin. If you specify an internal pin as being controllable, you need to ensure that this pin can be controlled for the duration of the test cycle. The tool will not validate your assumption.
#-domain => pecifies the DFT clock domain associated with the test clock.Clocks belonging to the same domain can be mixed in a chain. If you omit this option, a new DFT clock domain is created and associated with the test clock. Flip-flops belonging to different test clocks in the same domain can be mixed in a chain. Lockup elements can be added between the flip-flops belonging to different test clocks.
define_dft test_clock -name scan_clk -domain scan_clk -period 100000 -rise 40 -fall 80 SCLK => scan_clk defined at port SCLK with period of 100ns (10 Mhz). rise happens at 40% from start of clk period while fall happens at 80%. So, rise happens at 40ns, while fall happens at 80 ns, assuming clk starts at 0ns. This test clk can be referred to as scan_clk from now on (name is helpful to search for the test clk, or look it in reports, etc). We don't specify hookup_pin as in RTL, we force the i/p clk pin to goto all flops in scan_mode (by using mux).
#define_dft shift_enable -name <shiftEnableObject> -active <high|low> <portOrpin_name> -hookup_pin <pin_name> [-create_port] => It specifies name and active value for shift_en signal. Active value is propagated during dft rule checking. The input signal can be defined on a top-level port or an internal driving pin. hookup_pin is internal pin which is the actual scan_en that should goto all flops.
define_dft shift_enable -name scan_enable -active high SCAN_EN_IN => SCAN_EN_IN is defined as shift_enable and referred to as "scan_enable". In this RTL is coded so that scan_en_out comes back in as input port with name SCAN_EN_IN, so no need of hookup_pin.
#define_dft scan_chain -name <ChainName> -sdi <topLeveLSDIPort> -sdo <topLevelSDOPort> [-hookup_pin_sdi <coreSideSDIDrivingPin>] [-hookup_pin_sdo <coreSideSDOLoadPin>] [-shift_enable <ShiftEnableObject>] [-shared_output | -non_shared_output] [-terminal_lockup <level | edge>] => -hookup_pin_sdi/sdo specs core side hookup pin to be used for the scan data input/output signal during scan chain connection. -shift_enable designates chain specific SE signal, else default shift_enable signal used. -shared_output specs that a mux be inserted in the scan data path by the connect_scan_chains cmd since functional o/p port is being used as SDO port.
define_dft scan_chain -name chain1 -sdi spi_mosi -sdo spi_miso -shared_output => sdi and sdo defined
###end of scan_constraints.tcl file
# DFT DRC Checking
check_dft_rules > $_REPORTS_PATH/${DESIGN}_dft.rpt => look at hdl_track_filename_row_col attr.
report dft_registers >> $_REPORTS_PATH/${DESIGN}_dft.rpt
report dft_setup >> $_REPORTS_PATH/${DESIGN}_dft.rpt
check_design -multidriven
check_dft_rules -advanced >> $_REPORTS_PATH/${DESIGN}_dft.rpt
report dft_violations -tristate -xsource -xsource_by_instance >> $_REPORTS_PATH/${DESIGN}_dft.rpt
#fix dft violations before proceeding (either by modifying RTL or using auto fixing)
fix_dft_violations
# To turn off sequential merging on the design uncomment & use the following attributes.
set_attribute optimize_merge_flops false /
set_attribute optimize_merge_latches false /
#synthesize to map regular FF to scan FF (define_dft above makes forces synthesize cmd to include scan FF instead of non-scan FF. There is no separate scan option to synthesize with scan
synthesize -to_map -no_incr -auto_identify_shift_register => shift reg auto identified so that they are not replaced by scan cells
#Build the full scan chanins.
connect_scan_chains -preview => It shows how scan chain will be connected but makes no changes yet to the netlist.
connect_scan_chains -auto_create_chain => connects scan FF which pass DFT into scan_chain. -auto_create_chain option allows the tool to create more chains, if needed, than what has been specified thru define_dft cmd.
report dft_chains > $_REPORTS_PATH/${DESIGN}_SCAN_Chain.txt
delete_unloaded_undriven -force_bit_blast -all digtop => remove unconnected ports in the design
set_attribute remove_assigns true => remove assigns & insert tiehilo cells during Incremental synthesis
set_attribute use_tiehilo_for_const duplicate
#incremental synthesis only if needed
#synthesize -to_mapped -eff low -incr
#IMP: we might have 1'b0 and 1'b1 in logic after scan synth. To connect them to tiehi/tielo cells, run this:
insert_tiehilo -all -hilo TO020L -verbose [find -design *]
#reports after scan insertion
report dft_setup > $_REPORTS_PATH/${DESIGN}-DFTsetup_final
write_scandef > ${DESIGN}-scanDEF
#write_atpg [-stil|mentor|cadence] > ${DESIGN}-ATPG
write_atpg -stil > ${DESIGN}-ATPG
write_dft_abstract_model > ${DESIGN}-scanAbstract
write_hdl -abstract > ${DESIGN}-logicAbstract
write_script -analyze_all_scan_chains > ${DESIGN}-writeScript-analyzeAllScanChains
## check_atpg_rules -library <Verilog simulation library files> -compression -directory <Encounter Test workdir directory>
## write_et_bsv -library <Verilog structural library files> -directory $ET_WORKDIR
## write_et_mbist -library <Verilog structural library files> -directory $ET_WORKDIR -bsv -mbist_interface_file_di
r <string> -mbist_interface_file_list <string>
## write_et_atpg -library <Verilog structural library files> -compression -directory $ET_WORKDIR
write_et_atpg -library /db/pdk/lbc7/rev1/diglib/msl270/r3.0.0/verilog/models/*.v -directory $ET_WORKDIR
#final reports
generate_reports -outdir $_REPORTS_PATH -tag ${DESIGN}.scan
summary_table -outdir $_REPORTS_PATH
report timing -num_paths 500 >> $_REPORTS_PATH/${DESIGN}.all_timing.scan.rpt
foreach cg [find / -cost_group -null_ok *] {
report timing -cost_group [list $cg] -num_paths 100 > $_REPORTS_PATH/${DESIGN}_scan.[basename $cg]_timing.rpt
}
report area > $_REPORTS_PATH/${DESIGN}.scan.compile.rpt
report design_rules >> $_REPORTS_PATH/${DESIGN}.scan.compile.rpt
report summary >> $_REPORTS_PATH/${DESIGN}.scan.compile.rpt => reports area, timing and design rules.
#optional reports
report messages > $_REPORTS_PATH/${DESIGN}.scan.compile.rpt
report qor >> $_REPORTS_PATH/${DESIGN}.scan.compile.rpt
report gates -power >> $_REPORTS_PATH/${DESIGN}.scan.compile.rpt
report clock_gating >> $_REPORTS_PATH/${DESIGN}.scan.compile.rpt
report power -depth 0 >> $_REPORTS_PATH/${DESIGN}.scan.compile.rpt
report datapath > $_REPORTS_PATH/${DESIGN}.scan.compile.rpt
write_design -basename ${_OUTPUTS_PATH}/${DESIGN}_scan
write_script > ${_OUTPUTS_PATH}/${DESIGN}_scan.script
write_hdl > ${_NETLIST_PATH}/${DESIGN}_scan.v => final scan netlist
-- end of insert_dft.tcl
#write sdc and do files
write_sdc > sdc/constraints.sdc
#Write do file for RTL is to be compared with the final netlist. only revised is specified since RTL is taken as golden. Otherwise we need to specify "-golden_design <RTL_files>"
if {$SCAN_EXISTS} {
write_do_lec -revised_design ${_NETLIST_PATH}/${DESIGN}_scan.v -logfile ${_LOG_PATH}/rtl2final.lec.log > ${_OUTPUTS_PATH}/rtl2final.lec.do
write_et_atpg -library /db/pdkoa/1533c035/current/diglib/pml48/verilog/models => write Encounter Test ATPG scripts in et_scripts dir to generate patterns
} else {
write_do_lec -revised_design ${_NETLIST_PATH}/${DESIGN}.v -logfile ${_LOG_PATH}/rtl2final.lec.log > ${_OUTPUTS_PATH}/rtl2final.lec.do
}
puts "Final Runtime & Memory."
timestat FINAL
puts "============================"
puts "Synthesis Finished ........."
puts "============================"
#################################
#for scan mapping, use this section
#################################
define_dft test_mode -shared_in -active high $TESTSCANMODE
set_attribute dft_dont_scan true [find / -inst I_WRAPPER/scanmode_r*]
set_attribute dft_dont_scan true [find / -inst I_WRAPPER/clked_nt_result*]
define_dft shift_enable -name SE \
-active high \
-hookup_pin [find / -pin I_WRAPPER/SCANEN]\
[find / -port I_GPIO_Y[1]]
define_dft test_clock -name SCANCLOCK \
-period 100000 -fall 40 -rise 60 \
[find / -port I_GPIO_Y[0]]
#define_dft test_mode -scan_shift -name RESET -active high \
# [find / -port I_XRESET]
define_dft scan_chain -name chain1 \
-sdi [find / -port I_GPIO_Y[2]] \
-sdo [find / -port O_GPIO_A[3]] \
-hookup_pin_sdi [find / -pin I_WRAPPER/SI1] \
-hookup_pin_sdo [find / -pin I_WRAPPER/SO1] \
-shared_out
define_dft scan_chain -name chain2 \
-sdi [find / -port I_GPIO_Y[4]] \
-sdo [find / -port O_GPIO_A[5]] \
-hookup_pin_sdi [find / -pin I_WRAPPER/SI2] \
-hookup_pin_sdo [find / -pin I_WRAPPER/SO2] \
-shared_out
set_attribute dft_min_number_of_scan_chains 2 [find / -design $DIGTOPLEVEL]
#set_attribute dft_mix_clock_edges_in_scan_chains true [find / -design $DIGTOPLEVEL]
################################################################################
## dft_drc is used instead of check_test command
################################################################################
check_dft_rules > ./reports/check_dft_rules.rpt
############################################33
Scan mapping: converting flip-flops that pass TDRC.
Scan mapping: bypassed. You have to either
1) set attribute 'dft_scan_map_mode' to 'tdrc_pass' and run 'check_dft_rules' or
2) set attribute 'dft_scan_map_mode' to 'force_all'.
Scan mapping bypassed because no TDRC data is available: either command 'check_dft_rules' has not been run or TDRC data has been subsequently invalidated.
#for scan
connect_scan_chains
---------------------------------------------------------------------------
For synthesis which involves multiple power domains:
----------
read_power_intent -module TOP -cpf "../TOP.cpf"
redirect chk.cpf.detailed.rpt "check_cpf -detail"
commit_power_intent
verify_power_structure -lp_only -pre_synthesis -detail > $_REPORTS_PATH/digtop_verify_power.rpt
write_cpf -output_dir ${_OUTPUTS_PATH} -prefix ${DESIGN}_
write_power_intent -base_name ${_OUTPUTS_PATH}/TOP_m -cpf -design TOP