SDC constraint cmds

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Last Updated: Thursday, 26 September 2024 22:06

Published: Saturday, 13 May 2023 07:04

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SDC Synthesis Constraints:

SDC was developed mainly for Synthesis design constarints, but we saw above that a lot of other cmds got added over time. Below we see the design constraints that are standard in all synthesis tools now.
write_sdc is an sdc cmd that writes all constraints that the synthsis tool sees in the design (provided by the user in any format) in the sdc format. This file in sdc format can then be used as i/p to any other tool, that relies on sdc cmds. This is very useful when porting constraints. These are few SDC cmds that are provided to any design for synthesis:

1. Environment Constraints: external to design: op cond (PVT), WLM, load (both i/p and o/p), drive (only on i/p) and fanout(only on o/p).
2. Clocks (primary and generated clocks): clk pins, freq, uncertainty and drive.
3. Constraints: design and opt constraints. Mainly input and output delays.
4. False paths and multicycle paths: timing constraints
5. Case analysis (for functional and scan): global constraints. sets appr pins and nets to 0/1 to enable func or scan. needed only when scan present.
6. Misc: set_don_touch, set_dont_use: global constraints. not needed for PT.

1. Environment Constraints: op cond (PVT), WLM, load (both i/p and o/p), drive (only on i/p) and fanout(only on o/p).

1. op cond: set operating condition of design
   1. set_operating_conditions =>
2. wire load models (WLM): WLM are set based on how we want to model net delays.
   
   1. set_wire_load_model: used only when design is not in physical (DC-topo or RC Physical) mode. WLM estimates effect of wire length and Fanout on res, cap and area of net. No. of fanout determines net length based on fanout to length table. Which Fanout to length table to use is determined based on area of cell which drives the net. DC uses the cap/res to calc wire delay.
   2. NOTE: In .lib file, we specify wire load model and wire load selection for different area of cell. See in liberty.txt for details.
      1. set auto_wire_load_selection true
      2. set_wire_load_model "6K_3LM" => sets wire load model to something other than the default one set in .lib file
      3. set_wire_load_mode enlosed:  Setting enclosed wire load mode. We may set different wire load models for different hier cells. By setting this parameter, we help tool decide which wire load mode to pick for a net in a specific hier. allowed values are: top(default), enclosed, segmented. By setting to enclosed, Wire load model of the module that entirely encompasses the wire is used for each wire. This more realistic than the more conservation "top" mode (in top mode, WLM for top design is used for all nets). segmented mode is most accurate as it uses WLM for each segment of wire, depending on which design it lies in.
   3. set_wire_load_min_block_size
   4. set_wire_load_selection_group
3. load (on both i/p and o/p): set_load cmd sets load on i/p or o/p ports and nets in design. -min/max can be used for hold/setup. we need to set load on i/p ports when the driving_cell on i/p port is far away or has extra fanout, so wire/pin cap added on i/p port using this cmd. Usually we only specify load for o/p ports, as i/p ports don't branch out anywhere else, so no extra load.
   1. NOTE: set_load also applies on internal nets, and so will override internally calculated net load value. When using DC-TOPO, for each net, cap and resistance are estimated based on estimated physical layout. so, in DC-TOPO, when we write sdc using write_sdc, we get set_load and set_resistance for each internal net in the sdc file. Be careful, not to use this sdc file in PnR tools as EDI or timing tools as PT. In EDI, use report_ports to view cap on ports. For EDI, Cap is in units from tech lib. For DC, cap is in units of set_units, if specified, else from tech lib.
   2. ex: set_load -pin_load 4.1912 [get_ports n_puc_sync] => -pin_load implies that load value for the port should be treated as extrnal pin cap and -wire_load implies external wire cap, or tot cap (pin+wire) when nothing specified.
   3. ex: set_load 4.1912 [all_outputs] => sets load of 4.2 units (total cap=pin+wire) on all o/p ports.
      1. Cadence Synthesis RC cmd: set_attribute external_pin_cap 0.05 [all_outputs] => RC cmd for setting cap on all o/p ports. set_load is preferred cmd as it's sdc cmd.
4. drive on i/p: 2 cmds used here: set_driving_cell and set_drive/set_input_transition
   
   1. ex: set_driving_cell -lib_cell <cell_name> [ports] => Sets  attributes  on input or inout ports of the current design, specifying that a library cell or output pin of a  library  cell drives specified ports. last entry is the name of i/p or inout ports on which driving cells are to be placed. These driving cells are not actually put in the design, they are used to model what is driving the pins from external world.
   2. set_driving_cell -lib_cell IV110 [get_ports n_puc] => puts IV110 to drive port n_puc
      1. Cadence Synthesis RC equiv => set_attr external_driver [find /lib*/ -libcell IV110] [all_inputs]
   3. set_drive => to set drive resitance (res unit in .libfile, usually Kohm) directly on port. For clocks, set drive res to 0 (infinite drive), so that DC/RC doesn't put buffers on it.
      1. syntax: set_drive <port_list> <resistance> => sets resistance of external driver in units of .lib for that port
      2. ex: set_drive 0 clk1 => sets clk1 driver res to be 0 Kohms, i.e ideal driver (infinite drive)
         1. RC equiv => set_attr external_resistance 0 [clk1]
   4. set_input_transition => Alt to set_drive. Sets  the  max_transition_rise, max_transition_fall, min_transition_rise, or min_transition_fall attributes  to  the  specified input and inout ports. -min/max state whether it's to be applied for hold/setup. "0" implies infinite transition
5. fanout on o/p: set_fanout_load cmd is used to model expected FO load on o/p port. When synthesizing, DC tries to keep FO on o/p port (by adding FO specified on o/p  port plus FO presented internally by cells connected to o/p port) less than max_FO specified for the design.
   1. ex: set_fanout_load 4 {out1} => puts FO of 4 (unitless number) on out1.
   2. set_port_fanout_number
6. MISC: Many misc cmds which are not needed in regular synthsis flow.
   
   1. set_resistance => sets the back annotated resistance value, which enables the back-annotation of resistance value for nets in net_list. The  specified  value overrides the internally-estimated net resistance value, so use it carefully. To use diff value for min delay analysis (hold), and max delay analysis (setup), use -min/-max option
      1. ex: set_resistance -min 300 U1/U2/NET3 => sets a resistance of 300 units to be used for hold analysis on net U1/U2/NET3

2. design constraints:

1. Design rule constraints: set_min_capacitance, set_max_transition, set_max_fanout, set_max_capacitance, set_cell_degradation (usually in .lib). precedence of design rule const in DC: min_cap (highest priority), max_tran, max_FO, max_cap, cell_degrad (lowest priority). precednece can be changed by using set_cost_priority in DC.
   1. set_min_capacitance => sets min cap attr on i/p ports. This ensures that load driven by i/p port is not below a certain value. not set in std cell .lib file. min cap is usually the lowest cap value with which a cell has been characterized to operate.
   2. set_max_transition 4.0 [find design *] => sets  the  maximum  transition  time, on specified clocks, ports, or designs. set by default for all i/p pin of all the cells in .lib (using max_transition : 4.10;). We can override the one in lib by specifying it explicitly for i/p, o/p ports or designs.
      1. Ex: set_max_transition 5 [get_clocks Clk] => sets value of 5 on all pins belonging to "Clk" clock group. Needed in cases where there are multiple clocks running at diff freq, so transition requirement for each group might be diff.
   3. set_max_fanout 20 => default_max_fanout defines as 20 in top of .lib file. Then for o/p pin of some cells (as tie-hi/tie-lo cell TO020), we specify max_fanout to 50 (max_fanout : 50;) in .lib file. Can be specified on i/p ports or designs.
   4. set_max_capacitance => Sets  the  max_capacitance attribute to a specified value on the specified clocks, ports and designs.
      1. ex: set_max_capacitance 2.0 [current_design] => sets max cap of 2 units on all design. Not needed as it's set by default for o/p pin of all the cells in .lib (using max_capacitance : 0.21;). allows to control cap directly, while set_max_transition & set_max_fanout control cap indirectly.
   5. set_cell_degradation => some .lib contain cell degradation table that list the maximum capacitance that can be driven by a cell as a function of the transition times at the inputs of the cell.
2. Optimization constraints: defines goals for area, power and timing (clocks, clock skews, i/p delay, o/p delay). DC attempts to meet these goals, w/o violating design rule constraints.
   
   1. area const:
      1. ex: set_max_area 0 => tries to reduce area to min. Not supported by Cadence
   2. power const: max_dynamic_power and max_leakage_power (requires power compiler license). Not needed if no pwr const for design.
   3. timing const:
      1. set_input_delay: sets external i/p delay on i/p ports. The delay specified is the delay from the rising edge of specified clk. Default is rising edge of clk (may be changed via -clock_fall option). Assumption is that the specified clk is firing the i/p port and is taking the specified amount of time outside the block, before it gets to the i/p port.
         
         • set_input_delay 0.2 -clock clk1 [remove_from_collection [all_inputs] [get_ports {all_clocks}]] => sets 0.2 unit delay on all i/p pins (except clk ports) relative to clk1 (clk1 is imaginary clk that fires the imaginary flop that is firing the i/p pin. It's NOT the i/p clk port of DUT. Almost all the time, clk1 is chosen to be same as i/p clk port). By default, i/p delay is 0 if not specified. -max specifies that delay refers to longest path (i.e for setup calc), while -min is for shortest path (i.e for hold calc). If not specified, same delay is used for both setup/hold and rise/fall. Usually for spi/i2c etc signals, we specify diff min/max value as setup/hold numbers are different (we try to provide large setup delay and almost 0 hold delay). We can also specify rising/falling edge of clk.
           • ex: setup: set_input_delay -max 40 -clock spi_clk spi_cs_n => specifies a setup time of 10ns (assuming clk=50ns period, then 50-40=10ns of time available for internal ckt) for port "spi_cs_n". The port data is fired on rising edge of "spi_clk". Depending on how it's captured inside the chip, it may be full cycle orhaf cycle path.
           • ex: hold:  set_input_delay -min 0 -clock spi_clk spi_cs_n => specifies 0ns holdtime. "-min" is not needed in DC, as we don't run any hold timing optimization (as there are no clk tree buffers, clk is treated ideal). But it's needed to be used in PnR for the tool to work on this path to fix hold.
      2. set_output_delay: sets external o/p delay on o/p ports. The delay specified is the delay from the output port to the rising edge of specified clk. Default is rising edge of clk (may be changed via -clock_fall option). Assumption is that the specified clk is capturing the o/p port and is taking the specified amount of time outside the block, before it gets captured.
         
         • ex: set_output_delay -clock osc_clk -clock_fall 10  [get_ports {dout[65]}] => specifies o/p delay of 10ns wrt falling edge of osc_clk for port "dout[65]". By default, delay is wrt rising edge of clk.
         • ex: set the input and output delays for the bidirectional port INOUT1. The input signal arrives at INOUT1 2.5 units after the falling edge of CLK1. The output signal is required at INOUT1 at 1.4 units before the rising edge of CLK2.
           • set_input_delay 2.5 -clock CLK1 -clock_fall { INOUT1 }
           • set_output_delay 1.4 -clock CLK2 { INOUT1 }
      3. Optional ideal attr => not needed for clocks in synthesis tools (such as DC). clk nets are ideal nets by default.
         1. set_ideal_network {clk1 clk2} (added in sdc 1.7) => marks ports/pins (clk1, clk2) as src of ideal network. Ideal networks are an extension of ideal nets that incorporate automatic propagation  of  the  ideal  attribute. All nets, cells, and pins on the transitive fanout of these objects are treated as ideal. Propagation  traverses through combinational cells but stops at sequential cells. "-no_propagate" option prevents ideal propagation thru logic gates. In  addition  to disabling timing updates and timing optimizations, all cells and nets in the ideal network have the dont_touch attribute  set. The latency and transition times of an ideal network are 0 by  default, but   you   can  override  them  by  using  the  set_ideal_latency  and set_ideal_transition commands.
         2. set_ideal_latency 2 clk1 (added in sdc 1.7) => Specifies latency of 2 units for ideal network (clk1). By default, "0" ideal latency ias assumed for ideal networks.
         3. set_ideal_transition (added in sdc 1.7) =>
         4. set_dont_touch_network [get_clocks *] => dont_touch attributes is placed on all cells/nets in the transitive  fanout  of  dont_touch_network objects (clk, pins or ports). It's intended primarily  for clock circuitry. Placing a dont_touch_network on a clock object prevents the compile command from  modifying  the  clock  buffer network.

 
clock related:
-------------
create_clock

create_generated_clock

set_clock_gating_check

set_clock_latency

set_clock_transition

set_clock_uncertainty

set_propagated_clock

clock_group, path group cmds

timing exceptions:
-----------
set_false_path:

set_multicycle_path:

set_max_delay/set_min_delay

set_disable_timing
set_max_time_borrow

set_data_check

set_timing_derate
                           
3. global constraints:

These are extra constraints that we want the tool to adhere to.

1. set_dont_use => It says not to use certain lib cells in design.
   1. syntax: set_dont_use <libcell> <true/false> => sets dont_use attr on that libcell to true/false. default=true. true/false can also come before libcell, i.e: set_dont_use  <true/false> <libcell>. NOTE: set_dont_use isn't supported in PT.
      1. set_dont_use [get_lib_cells CGP*] FALSE  => sets clk gating attr dont_use to false => use CGP cells. We can use "list" to get all cells in a particular library "set_dont_use [list PML30_W_150_1.65_CTS.db/CGP*] FALSE", but this won't work in RC, as list is not sdc cmd.
         1. RC equiv => set_attr avoid 0 [find /lib* -libcell CGP*]  => 0/false means use it.  1/true means dont use. NOTE: PML30*.db lib exist in /libraries/MSL* virtual dir structure in RC, so, we have to use find in /libraries/. We could use dc::get_lib_cells also in RC. ex:
            1. set_attr avoid 0 [dc::get_lib_cells PML30*/CGP*] => finds all CGP* cells in any subdir with PML30* name in top virtual dir.
            2. set_attr avoid 0 [dc::get_lib_cells CGP*] => finds all CGP* cells in all dir/subdir in virtual dir /libraries/MSL270_W_125_2.5_CTS.db/libcells/CGP40, etc.
2. set_dont_touch => This specifies not to touch this object. This may be needed when we have an instance in RTL that is already speciifed as a std cell from lib, and we don't want synthesis tool to mess with it.
   
   1. syntax: set_dont_touch {<design> | <subdesign> | <instance> | <net> | <libcell>} => keeps that object.
      1. ex: set_dont_touch Imtr_a/hs_buf => keeps hs_buf in design as it is. However, nets connected to this buf can be optimized away. To keep the nets untouched too, use this:
      2. ex: set_dont_touch [get_nets -of_objects [get_cells {Imtr_a/hs_buf}]] => all nets connected to hs_buf set to dont_touch. this needed to prevent nets of that cell from getting removed. Otherwise the cell may be there, but it's i/p, o/p nets may be optimized away.
         1. RC equiv => set_attr preserve 1 Imtr_a/hs_buf => .  1/true means dont touch. 0/false means the tool is free to modify it (which is the default case)
3. set_case_analysis:
4. set_logic_dc,set_logic_one, set_logic_zero