spef

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Last Updated: Friday, 12 October 2018 04:25

Published: Friday, 12 October 2018 04:25

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SPEF: this file has Res,Cap and other parasitic info for all nets in design
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Standard Parasitic Exchange Format (SPEF) is an IEEE standard for representing parasitic data of wires in a chip in ASCII format. Resistance, capacitance and inductance of wires in a chip are known as parasitic data. SPEF is most popular specification for parasitic exchange between different tools of EDA domain during any phase of design.
The specification for SPEF is a part of standard 1481-1999 IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System.

General Syntax
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A typical SPEF file will have 4 main sections:
¡V a header section,
¡V a name map section,
¡V a top level port section and
¡V the main parasitic description section.

Generally, SPEF keywords are preceded with a *. For example, *R_UNIT, *NAME_MAP and *D_NET.
Comments start anywhere on a line with // and run to the end of the line. Each line in a block of comments must start with //.


A. Header Information
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The header section is 14 lines containing information about
¡V the design name,
¡V the parasitic extraction tool,
¡V naming styles
¡V and units.

When reading SPEF, it is important to check the header for units as they vary across tools.

ex: digtop.spef file:
--
*SPEF "IEEE 1481-1998"
*DESIGN "digtop" <design name
*DATE "Mon Mar 12 12:11:11 2012"
*VENDOR "Silicon Perspective, A Cadence Company"
*PROGRAM "Encounter"
*VERSION "09.12-s159_1"
*DESIGN_FLOW "COUPLING C" "PIN_CAP NONE" "NAME_SCOPE LOCAL"
*DIVIDER /
*DELIMITER :
*BUS_DELIMITER []
*T_UNIT 1 NS <= time units is ns
*C_UNIT 1 PF <= cap unit is pf
*R_UNIT 1 OHM <= res unit is ohm
*L_UNIT 1 HENRY <= ind unit is H

B. Name Map Section: optional
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To reduce file size, SPEF allows long names to be mapped to shorter numbers preceded by a *. This mapping is defined in the name map section.
ex:
--
*NAME_MAP

*1 spr_6/FE_OFCN92_tie_hi_net0 <= net name mapped. Later in the file, it can be refrred by *1
*2 spr_6/FE_OFCN93_tie_hi_net0
*2246 trim_dout[52]
*3062 U57 <= instance name mapped

C. Port Section
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The port section is simply a list of the top level ports in a design. They are also annotated as input, output or bidirect with an I, O or B.
ex:
--
*PORTS

*1973 I *C 0 2069 => *1973 is n_puc i/p pin.
*1975 I *C 185.9 2073.6

D. Parasitics: this is the main section. It has info about each and every net is design.
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Each extracted net will have a *D_NET section. This will usually consist of a *D_NET line, a *CONN section, a *CAP section, *RES section and a *END line. Single pin nets will not have a *RES section. Nets connected by abutting pins will not have a *CAP section.
The *D_NET line tells the net name and the net's total capacitance. This capacitance will be the sum of all the capacitances in the *CAP section.

ex:
--
*D_NET *1 0.163578 => net name is *1 and total cap on this net is 0.16pf = 160ff. Each net is subdivided into nodes with node id, which are used in cap and res fields below.

*CONN => lists all the pins connected to the net. A connection to a cell instance starts with a *I. A connection to a top level port starts with a *P. The syntax of the *CONN entries is:
*I <pin name> <direction> *C <xy coordinate> *L <load_pin_cap> *D <load_cell_type>

*I *2453:CLK I *C 493 1783 *L 0.00608 *D DTB20 => net *1 is connected to pin "clk" of instance *2453. clk is located at coord <493,1783>.  clk pin cap is 6ff and it's on cell DTB20.
...
*I *2323:A I *C 368 1943 *L 0.0129 *D BU140

*CAP => provides detailed capacitance information for the net. Entries in the *CAP section come in two forms, one for a capacitor lumped to ground and one for a coupled capacitor.
A capacitor lumped to ground has three fields: an identifying integer, a node name and the capacitance value of this node
A coupling capacitor has four fields: an identifying integer, two node names and the coupling capacitor values between these two nodes

1 *2323:A 9.27572e-05 => This lumped cap is given id 1, it's cap of 0.09ff to pin A of inst *2323
...
115 *2447:A *1707:33 0.000475296 => this coup cap is b/w pin A of *2447 and node id 33 of *1707(o/p buf x4).

*RES => provides the resistance network for the net. The resistance network for a net can be very complex.
Entries in *RES section contain 4 fields: an identifying integer, two node names and the resistance between these two nodes. Out of the 2 nodes, one of the node has to be the node for this net itself. The other node can be end point connection (any load in *conn) or other node on this net itself.

1 *1:19 *1:27 38.7104 => res of 38.7ohm b/w node id 19 and 27 of *1(this net).
...
46 *3565:Y *1:46 8 => res of 8ohm b/w node id 46 of this net and pin Y of *3565

*END => end of NET *1

*D_NET *2 0.0863349 <= repeat same as above for net *2
...
*END

*D_NET *2311 0.0154887 <= repeat same as above for all nets
...
*END

----------------------------------------------------
sample ex of a net:

*D_NET *2311 0.0154887 => net name *2311(wr_strobe_spi_sync). total cap=15.5ff which is the sum of all cap in *CAP. From digtop_route.v, we see that wr_strobe_spi_sync has following connections:
load1: NO210 U4 (.Y(n1), .B(n20), .A(wr_strobe_spi_sync));
driver: DTCD2 wr_strobe_spi_sync_reg (.Q(wr_strobe_spi_sync), .D(N28), .CLRZ(nreset), .CLK(clkosc__L2_N4));
load2: NO211 U161 (.Y(N28), .B(wr_strobe_spi_sync), .A(wr_strobe_spi_meta));
load3: IV110 U162 (.Y(n18), .A(wr_strobe_spi_sync));
load4: AN2D0 U176 (.Y(N145), .B(wr_strobe_spi_sync), .A(n193));

*CONN => there are 4 loads and 1 driver connected to this net.
*I *3556:B I *C 610 1416 *L 0.00265 *D AN2D0 => load4 is pin B of *3556(AN2D0). pin cap=2.6ff.
*I *3549:A I *C 540 1443 *L 0.00638 *D IV110 => load3 is pin A of *3549(IV110). pin cap=6.4ff.
*I *3548:B I *C 591 1416 *L 0.00561 *D NO211 => load2 is pin B of *3548(NO211). pin cap=5.6ff.
*I *3195:A I *C 588 1404 *L 0.00568 *D NO210 => load1 is pin B of *3195(NO210). pin cap=5.7ff.
*I *3220:Q O *C 622 1400 *L 0 *D DTCD2 => driver is pin Q of *3220(DTCD2). pin cap=0ff as it's o/p pin, even though in cap section, cap of 0.8+1.1+1=2.9ff is assigned to this o/p pin Q.

Now, this net (wr_strobe_spi_sync) is subdivided into subnets and node numbers are assigned to end points of these subnets. That forms a tree. Node ID appear in the connection part of cap and res section. If you look in connections of *RES section, you'll see that Node numbers are 5,6,7,8,9,10,11 (7 nodes) while the 11 res connecting these nodes and load/driver have been assigned 11 ids. Similarly in *CAP section, you will see that these 7 nodes are being used to connect coup/lump caps to, along with coup/lump caps attached to load, while 17 caps have been assigned 17 ids.
NOTE: Id of Res or cap have nothing to do with node numbers. Node numbers are the ones that form tree. Id for res and cap just indicate that particular cap/res were assigned some id. Same node numbers will appear in both res and cap section.
Below, a tree is formed as shown starting from driver o/p Q, and ending at 4 loads, ld1 to ld4. Node Ids 5 to 11 are shown.
Q->5->6->     10->     8->9->7->ld1
      6->ld4  10->ld2     9->11->ld3

*CAP => this section contains cap at each node and at some loads. Some loads are missing, not sure why?
top 10 are lumped cap, while 11 to 17 are coupling cap. These coupling cap are treated appr when running timing for setup/hold. In PT/ETS, all coupling cap are grounded to 0. So, it may be optimistic or pessimistic for setup/hold depending on which data or clock path it appears on. Ideally for setup, data path coup cap should be mult by 2, and clk path coup cap mult by 0, while for hold data path coup cap mult by 0, and clk path coup cap mult by 2. In PTSI, it does it that way.

1 *3220:Q 0.000805389 => driver o/p lump cap is 0.8ff. cap placed at o/p Q.
2 *3548:B 0.000700078 => lump cap placed at ld2
3 *3556:B 0.000671207 => lump cap placed at ld4
4 *2311:11 0.00116516 => lump cap placed at nodes 5 to 11
5 *2311:10 0.00159617
6 *2311:9 0.000124281
7 *2311:8 0.000102239
8 *2311:7 0.00367203
9 *2311:6 0.000747997
10 *2311:5 0.000117708
11 *2311:7 *3219:CLK 0.000676197 => coupling cap to clk of *3219 at node 7 of wr_strobe_spi_sync
12 *3220:Q *1929:10 0.00112872 => coupling cap to node 10 of *1929 placed at o/p Q.
13 *2311:7 *1762:7 0.000385412
14 *3556:B *170:8 0.000849882 => coupling cap to node 8 of *170 placed at ld4
15 *3556:B *3246:D 0.00124761 => coupling cap to pin D of *3246 placed at ld4
16 *2311:7 *1964:18 0.000400017
17 *3220:Q *1972:163 0.00109857 => coupling cap to node 163 of *1972 placed at o/p Q.

*RES => this section will contain all load and driver, as there has to be a res to the final end point. So, starting from driver, we can form a tree to all the loads:

1 *2311:8 *2311:10 8.80112
2 *3549:A *2311:7 17.2017
3 *2311:8 *2311:9 0.839437 => res b/w node id 8 and 9
4 *3556:B *2311:6 17.2017
5 *2311:9 *2311:11 11.3902
6 *3195:A *2311:11 8.16737 => res b/w node id 11 and ld3
7 *3548:B *2311:10 9.20169
8 *2311:5 *2311:6 2.04502
9 *2311:7 *2311:9 8.07294
10 *2311:6 *2311:10 11.2614
11 *3220:Q *2311:5 19.0042
*END

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