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Details: Last Updated: Friday, 12 October 2018 04:54; Published: Friday, 12 October 2018 04:54; Hits: 1377

DEF: design exchange format.
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has logical design data (netlist) and physical design data (routing, placement location,etc).
most of the file syntax same as that for LEF

#def file => comments preceded by #
VERSION 5.7 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN digtop ;
UNITS DISTANCE MICRONS 2000 ; => Specifies the convert factor used to convert DEF distance units into LEF distance units. 2000 implies that 1 micron in lef file is equiv to 2000 database units (dbu) in def file. All unnits in def file are in terms of dbu. Allowed values for dbu are 100, 200, 1000, 2000.

PROPERTYDEFINITIONS
    COMPONENTPIN designRuleWidth REAL ;
    DESIGN FE_CORE_BOX_LL_X REAL 25.500 ;
    DESIGN FE_CORE_BOX_UR_X REAL 881.300 ;
    DESIGN FE_CORE_BOX_LL_Y REAL 27.200 ;
    DESIGN FE_CORE_BOX_UR_Y REAL 829.600 ;
END PROPERTYDEFINITIONS

DIEAREA ( 0 0 ) ( 1813000 1713200 ) ; => coord of die in dbu

ROW: shows all rows that are there. Each row has a name.
---
syntax: ROW <row_name> <row_type> <origin_X origin_Y> <orientation> {DO x BY 1 STEP <sp_x 0> or DO 1 BY y STEP <0 sp_y> } => in x BY y, if x=1, it's vertical row. if y=1, it's horizontal row. Mostly designs have horizontal rows, so y=1. x then denotes the number of repeating columns that create this row. sp_x denotes spacing_b/w_cols_in_horizontal_row, while sp_y denotes spacing_b/w_rows_in_vertical_cols.

ex:
ROW CORE_ROW_0 CORESITE 51000 54400 FS DO 503 BY 1 STEP 3400 0 ; => row "CORE_ROW_0" present in site "CORESITE" with origin (51000,54400) dbu (=51000/2000,54400/2000 = 25.5um,27.2um). orientation is flip south. this row has 503 cols, where each col has 3400 dbu of spacing. 3400 spacing is taken from M2 pitch in tech lef file (M2 pitch=1.7um in tech lef file, which translates to 3400 dbu). So, each row has a width of 503x3400=1710200, add left and right offset of 51000 and we get the x dimension of die to be 1813000.
similarly for next row and so on ...
ROW CORE_ROW_39 CORESITE 51000 1632000 N DO 503 BY 1 STEP 3400 0 ;

TRACKS: tracks defined for each metal layer in both x and y dirn. router can only route on tracks.
------
syntax: TRACKS {X | Y} <start> DO numtracks STEP space [LAYER layerName] ; => X indicates vertical lines, while Y indicates horizontal lines. start is the x or y coord of first line. space indicates spacing b/w tracks, We specify both horizontal and vertical tracks for each metal layer.
TRACKS X 3400 DO 533 STEP 3400 LAYER MET3 ; => vertical lines for met3 starting from 3400dbu, repeat it 533 times with spacing of 3400 dbu.
TRACKS Y 3400 DO 503 STEP 3400 LAYER MET3 ; => similarly horizontal lines for met3.
TRACKS Y 3400 DO 503 STEP 3400 LAYER MET2 ;
TRACKS X 3400 DO 533 STEP 3400 LAYER MET2 ;
TRACKS X 3400 DO 533 STEP 3400 LAYER MET1 ;
TRACKS Y 3400 DO 503 STEP 3400 LAYER MET1 ;

GCELLGRID: Defines the gcell grid for a standard cell-based design.
---------
Each GCELLGRID statement specifies a set of vertical (X) and horizontal (Y) lines, or tracks, that define the gcell grid. You select a gcell grid based on routing resources for the floorplan. Every track segment must belong to a gcell. The gcell grid partitions the routing portion of the design into rectangles, called gcells. A gcell grid in which all gcells are the same size is called a uniform gcell grid, otherwise it's a non-uniform grid.

syntax: GCELLGRID {X <start> DO numColumns+1 STEP space} {Y <start> DO numRows+1 STEP space} ; x=vertical, y=horizontal. space specifies spacing b/w tracks.

ex: There are 3 diff gcells formed below. 1st is gcell of size=800x31800, 2nd is gcell of size=(44x3400)x(121x3400), 3rd is gcell of size=3400x3400. so, everything inside the core is a uniform grid.
NOTE: GCELLGRID stmt keeps on getting modified at different stages of PnR flow by the routing tool, so that it works with optimal grid size. In the ex below, final gcell grid used insixde core was 64000x64000 (i.e 400 times of initial gcell grid size)

GCELLGRID X 1499400 DO 2 STEP 800 ; => starts at (1499400,4117400) and forms 1 gcell grid of size=800x31800
GCELLGRID Y 4117400 DO 2 STEP 31800 ;

GCELLGRID X 3400 DO 45 STEP 34000 ; => starts at (3400,3400) and forms 44x121 gcell grid of size=3400x3400
GCELLGRID Y 3400 DO 122 STEP 34000 ;

GCELLGRID X 0 DO 2 STEP 3400 ; => starts at (0,0) and forms 1 gcell grid of size=3400x3400
GCELLGRID Y 0 DO 2 STEP 3400 ; =>

VIAS: same as in lef file (these vias are defined in def file so that they can be referenced locally from here, wherever they are used. If they are not not defined here, then during import of def file in virtuoso, tool will try to see if these exist in Tech library. If yes, then it will map these vias with those present in tech library, else it will give an error "via not found" and drop the vias from imported layout).
----
- VIAS12 => defines a single via b/w M1 and M2. This via is defined in tech lef file. Since units is 2000 in lef file, all dimensions in lef file are multiplied by 2000. So, VIAS12 M1 rect of (-0.25 -0.35 0.25 0.35) gets translated into (-0.25*2000 -0.35*2000 0.25*2000 0.35*2000) = (-500 -700 500 700)
+ RECT METAL1 ( -500 -700 ) ( 500 700 )
+ RECT METAL2 ( -500 -500 ) ( 500 500 )
+ RECT VIAS1 ( -300 -300 ) ( 300 300 )

- VIAS12A => variation of via12. This via is rotated version of VIAS12, so that's it's longer in X, and shorter in Y.
+ RECT METAL1 ( -700 -500 ) ( 700 500 )
+ RECT METAL2 ( -500 -500 ) ( 500 500 )
+ RECT VIAS1 ( -300 -300 ) ( 300 300 )
;

- VIAGEN12_3 => This via was generated in tech lef file using "VIARULE VIAGEN12 GENERATE". This is used for vias in power ring vdd/vss. It has a array of 14 vias spread over M1/M2 and named as VIAGEN12_3. Other shapes of vias that are generated for vdd/vss at the corner is named VIAGEN12_1, etc. These are instantiated in special nets section below.
+ PATTERNNAME VIAGEN12_5.0000_2.0000_I7F
+ RECT METAL1 ( -5000 -2000 ) ( 5000 2000 )
+ RECT METAL2 ( -5000 -2000 ) ( 5000 2000 )
+ RECT VIAS1 ( -4500 -1000 ) ( -3900 -400 )
+ RECT VIAS1 ( -4500 400 ) ( -3900 1000 )
+ ..... => 14 such vias spread on metal1/metal2
+ RECT VIAS1 ( -3100 -1000 ) ( -2500 -400 )
;
END VIAS

-- VIAGEN12_3 can also be defined as viarule instead of specifying 14 vias separately. This makes it more compact, but then these custome vias might not get generated correctly during def import to icfb. See in cadence_virtuoso.txt for more details.
- VIAGEN12_4
+ VIARULE VIAGEN12G => here viarule specified for generating this via "VIAGEN12_4" using viarule VIAGEN12G. This viarule "VIAGEN12G" needs to be defined either here or should exist in virtuose tech library, else we'll get error about "missing via defn" during def import to icfb.
+ CUTSIZE 300 300
+ LAYERS MET1 VIA1 MET2 => layers specified
+ CUTSPACING 550 550 => spacing b/w vias
+ ENCLOSURE 600 600 600 600 => overhang on all sides b/w cut layer and metal layer
+ ROWCOL 1 11
;

COMPONENTS: placement info of all stdcells
---------
COMPONENTS 1694 ; => 1694 total components
- spr_0/FE_OFCC104_tie_hi_net0 BU170 + SOURCE TIMING + PLACED ( 1043800 860200 ) N ; => initially all cells are unplaced. PLACED impliesit's placed and component's location can be moved by automatic tools while FIXED implies component's location cannot be moved by automatic tools. We always provide location co-ordinates and orientation. Co-ordinates are always specified for the lower left corner of cell, irrespective of orientation. N=North, FN=flipped North. N,S,E,W refer to rotation at origin in clockwise dirn, while FN,FS,FE,FW refer to flipping across y axis.
#N=>cell placed normally (crossbar on bottom left, so VDD on top and VSS on bottom)),
#E=>crossbar on top left. It's N rotated by 90 degrees clockwise so that VSS is on left side while VDD is on right side. Normally this orientation does not apply to stdcells but to routes.
#S=>crossbar on top right, so VSS on top and VDD on bottom, S is N rotated 180 deg clockwise),
#W=>crossbar on bottom right. It's N rotated by 270 degrees clockwise (or 90 degrees anti-clockwise) so that VSS is on left side while VDD is on right side. Normally this orientation does not apply to stdcells but to routes.
- FILLER_2173 FILLER2 + SOURCE DIST + PLACED ( 241400 4097000 ) FS .... ;
- Imtr_b/hs_pos_tmp_dly_clk_reg_0 DTCD2 + FIXED ( 1332800 3199400 ) FS + WEIGHT 1 ;
END COMPONENTS

PINS:
----
PINS 411 ;
- n_puc + NET n_puc + DIRECTION INPUT + USE SIGNAL
+ LAYER MET2 ( -2000 0 ) ( 0 2000 )
+ FIXED ( 0 4138000 ) E ;
- ...
- ana_sel_native + NET ana_sel_native + DIRECTION OUTPUT + USE SIGNAL
+ LAYER MET2 ( 0 0 ) ( 2000 2000 )
+ FIXED ( 590200 0 ) N ;
;
END PINS

SPECIALNETS: used for pwr/gnd. These VDD/VSS pins are present for all stdcells in lef file, where PIN VDD has "USE POWER", while PIN VSS has "USE GROUND". So, PnR is able to connect pwr/gnd pins of stdcells correctly to VDD/VSS routes in floorplan.
----------
SPECIALNETS 2 ;
- VSS
+ ROUTED MET1 7600 + SHAPE FOLLOWPIN ( 17000 207400 ) ( 1482400 * )
     NEW MET1 7600 + SHAPE FOLLOWPIN ( 17000 125800 ) ( 1482400 * )
     ...
+ USE GROUND ;
- VDD
   + ROUTED MET1 7600 + SHAPE FOLLOWPIN ( 17000 17000 ) ( 1482400 * )
     NEW MET1 7600 + SHAPE FOLLOWPIN ( 17000 71400 ) ( 1482400 * )
     ...
   + USE POWER ;
END SPECIALNETS

NETS
---
NETS 2941 ; => total no. of nets is 2941
- dcdc_ldo_00/FE_PHN147_N46 => name of the net is dcdc_ldo_00/FE_PHN147_N46
( dcdc_ldo_00/FE_PHC147_N46 Y ) ( dcdc_ldo_00/FE_PHC140_N46 A ) => component pin names
#now wiring specified by + COVER | + FIXED | + ROUTED | + NOSHIELD
+ ROUTED MET1 ( 314300 1098300 ) ( 315700 * 0 ) => + ROUTED means wiring can be moved by tool. It's routed on MET1 with the rectangular co-ords given. co-ords are for centerline of wire. The wire is 1/2 width on one side and 1/2 width on other side. "*" specifies that the y-coord last specified is used. So, here,* means 1098300. The third value of 0 specifies how far the wire is extended at specified point (default is half the routing width for that layer). so, be default, wire is extended 1/2 width on both the end points of center line. If value was 5, then wire is extended 1/2 routing width + 5 units.
    NEW POLY ( 314300 1098300 ) ( * 1105300 ) CONTSPLY1 => NEW indicates a new wire segment, i.e there's NO wire segment b/w last specified segment and next coord. CONSTPLY1 implies there is a via "CONTSPLY1" at the last specified coord. * means x-coord is 314300.
    NEW MET1 ( 314300 1105300 ) ( 315700 * ) VIAS12
    NEW MET2 ( 315700 1105300 ) ( 317100 * )
    NEW MET2 ( 317100 1085700 ) VIAS12 => if only one co-ord specified, it's just a point in MET2 (it's width * width square since it's extended on all sides). VIAS12 is placed on this MET2 wire.
    NEW MET5 0 + SHAPE BLOCKWIRE ( 557000 748375 ) VIAGEN45_22 => here loc of generated via is specified. so, this via defined above will beplaced here.
    NEW MET5 750 ( 1375 0 ) ( * 749750 )
+ SOURCE TIMING
;
- Idigital_mux/n154 ...;
END NETS

--------
ENDDESIGN => ends design digtop def file

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