lef
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LEF : library exchange format - developed by cadence
-----------------------------
An ASCII data format, used to describe a standard cell library. Includes the design rules for routing and the Abstract of the cells, no information about the internal netlist of the cells. Usually kept as 2 files, a tech lef file, and a design lef file.
A LEF file contains the following sections:
1. Technology: layer, design rules, via definitions, metal capacitance
2. Site: Site extension
3. Macros: cell descriptions, cell dimensions, layout of pins and blockages, capacitances.
1. The technology is described by the Layer and Via statements. To each layer the following attributes may be associated:
-type: Layer type can be routing, cut (contact), masterslice (poly, active), overlap.
-width/pitch/spacing rules
-direction
-resistance and capacitance per unit square
-antenna Factor
Manufacturing Grid: Defines the manufacturing grid for the design. The manufacturing grid is used for
geometry alignment. When specified, shapes and cells are placed in locations that
snap to the manufacturing grid.
MANUFACTURINGGRID value ;
I. Layers are defined in process order from bottom to top
poly masterslice
cc cut
metal1 routing
via cut
metal2 routing
via2 cut
metal3 routing
A. Cut Layer definition: Defines contact layer (top layer and bottom layer) for via
LAYER layername
TYPE CUT;
SPACING => Specifies the minimum spacing allowed between via cuts on the same net or different nets. This value can be overridden by the SAMENET SPACING statement (we are going to use this statement later)
END layerName
B. Implant Layer definition: Defines implant layers in the design. Each layer is defined by assigning it a name and simple spacing and width rules. These spacing and width rules only affect the legal cell placements. These rules interact with the library methodology, detailed placement, and filler cell support.
LAYER layerName
TYPE IMPLANT ;
SPACING minSpacing
END layerName
C. Masterslice or Overlap Layer definition: Defines masterslice (nonrouting) or overlap layers in the design.
Masterslice layers are typically polysilicon layers and are only needed if the cell MACROs have pins on the polysilicon layer.
Overlap layer is used for overlap checking for rectilinear blocks (i.e L shaped blocks). Obstruction descriptions in the macro obstruction statements refer to the overlap layer
LAYER layerName
TYPE {MASTERSLICE | OVERLAP} ;
...
D. Routing Layer definition
LAYER layerName
TYPE ROUTING ;
DIRECTION {HORIZONTAL | VERTICAL} ;
PITCH distance;
WIDTH defWidth;
OFFSET distance ;
SPACING minSpacing;
RESISTANCE RPERSQ value ; => Specifies the resistance for a square of wire, in ohms per square. The resistance of a wire can be defined as RPERSQU x wire length/wire width
CAPACITANCE CPERSQDIST value ; => Specifies the capacitance for each square unit, in picofarads per square micron. This is used to model wire-to-ground capacitance.
II. Via: Defines vias for usage by signal routers. Default vias have exactly three layers used: a cut layer, and two layers that touch the cut layer (routing or masterslice). The cut layer rectangle must be between the two routing or masterslice layer rectangles.
VIA viaName DEFAULT TOPOFSTACKONLY
FOREIGN foreignCellName [pt [orient]] ;
RESISTANCE value ;
{LAYER layerName ; => layer1, layer2 and cut layer specified here
{RECT pt pt ;} ...} ...
END viaName
Via Rule Generate: Defines formulas for generating via arrays. Use the VIARULE GENERATE statement to cover special wiring that is not explicitly defined in the VIARULE statement. Rather than specifying a list of vias, we can specify viarule to generate cut layer geometries.
VIARULE viaRuleName GENERATE
LAYER routingLayerName ; => layer1
{ DIRECTION {HORIZONTAL | VERTICAL} ;
OVERHANG overhang ;
METALOVERHANG metalOverhang ;
| ENCLOSURE overhang1 overhang2 ;}
LAYER routingLayerName ; => layer2
{ DIRECTION {HORIZONTAL | VERTICAL} ;
OVERHANG overhang ;
METALOVERHANG metalOverhang ;
| ENCLOSURE overhang1 overhang2 ;}
LAYER cutLayerName ; => cut layer
RECT pt pt ;
SPACING xSpacing BY ySpacing ;
RESISTANCE resistancePerCut ;
END viaRuleName
Same-Net Spacing: Defines the same-net spacing rules. Same-net spacing rules determine minimum spacing between geometries in the same net and are only required if same-net spacing is smaller than different-net spacing, or if vias on different layers have special stacking rules.
These specifications are used for design rule checking by the routing and verification tools.
Spacing is the edge-to-edge separation, both orthogonal and diagonal.
SPACING
SAMENET layerName layerName minSpace [STACK] ; ...
END SPACING
------
2. Site
SITE siteName
CLASS {PAD | CORE} ;
[SYMMETRY {X | Y | R90} ... ;] (will discuss this later in macro definition)
SIZE width BY height ;
END siteName
------
3. Macro
MACRO macroName
[CLASS
{ COVER [BUMP]
| RING
| BLOCK [BLACKBOX]
| PAD [INPUT | OUTPUT |INOUT | POWER | SPACER | AREAIO]
| CORE [FEEDTHRU | TIEHIGH | TIELOW | SPACER | ANTENNACELL]
| ENDCAP {PRE | POST | TOPLEFT | TOPRIGHT | BOTTOMLEFT | BOTTOMRIGHT}
}
;]
[SOURCE {USER | BLOCK} ;]
[FOREIGN foreignCellName [pt [orient]] ;] ...
[ORIGIN pt ;]
[SIZE width BY height ;]
[SYMMETRY {X | Y | R90} ... ;]
[SITE siteName ;]
[PIN statement] ...
[OBS statement] ...
Macro Pin Statement
PIN pinName
FOREIGN foreignPinName [STRUCTURE [pt [orient] ] ] ;
[DIRECTION {INPUT | OUTPUT [TRISTATE] | INOUT | FEEDTHRU} ;]
[USE { SIGNAL | ANALOG | POWER | GROUND | CLOCK } ;]
[SHAPE {ABUTMENT | RING | FEEDTHRU} ;]
[MUSTJOIN pinName ;]
{PORT
[CLASS {NONE | CORE} ;]
{layerGeometries} ...
END} ...
END pinName]
Macro Obstruction Statement
OBS
{ LAYER layerName [SPACING minSpacing | DESIGNRULEWIDTH value] ;
RECT pt pt ;
POLYGON pt pt pt pt ... ;
END
-----------------------
TI tech lef file: pml30_lbc8_tech_3layer.lef
It has general info, then defines layers, vias, viarules, and lastly spacing
VERSION 5.4 ;
NAMESCASESENSITIVE ON ;
BUSBITCHARS "[]" ;
DIVIDERCHAR "/" ;
UNITS
DATABASE MICRONS 2000 ; => conversion factor from lef to def is 2000. means numbers in lef file should be multiplied by 2000 before being used in def file.
END UNITS
MANUFACTURINGGRID 0.100 ;
--overlap layer --
LAYER OVERLAP
TYPE OVERLAP ;
END OVERLAP
#poly and cont layers are there only in lbc5 and earlier tech files for 2 metal layer files. Router routes on all layers in the tech lef file that have "TYPE ROUTING", so, router will start from default bottom layer, which may be POLY or MET1, depending on this file.
--poly and CONT layer --
LAYER POLY
TYPE ROUTING ;
...
END POLY
LAYER CONT
TYPE CUT ;
SPACING 0.7 ; => min spacing b/w vias is 0.7um
END CONT
--metal1 layer --
LAYER MET1
TYPE ROUTING ;
ANTENNAAREARATIO 100.0 ; => max legal ant ratio, using area of metal wire that is not connected to diffusion diode
ANTENNADIFFAREARATIO PWL ( ( 1 1000 ) ( 100 10000 ) ( 500 50000 ) ) ; => Specifies the antenna ratio, using the area of the metal wire connected to the diffusion diode. You can supply an explicit ratio value or specify piece-wise linear format (PWL (diff_area1 ratio1) (diff_area2 ratio2) .. ), in which case the ratio is calculated using linear interpolation of the diffusion area and ratio input values. So in our ex, it means that if diffusion area of 1 is connected to the metal wire, then a ratio of 1000 should be used instead of a ratio of 100. If diffusion area of 100 is connected to the metal wire, then a ratio of 10000 should be used and so on. Note that with diffusion diode connected, antenna ratio is not infinity, as a diff diode can only allow so much current to pass thru it.
DIRECTION HORIZONTAL ;
PITCH 1.7 ;
OFFSET 0 ;
WIDTH 0.6 ; => M1 width is 0.6, but M2 and M3 width is 0.8
SPACING 0.7 ; => min spacing is 0.7um for wires less than 15um wide for M1,M2,M3.
SPACING 1.5 RANGE 15 9999 ; => min spacing is 1.5 (instead of 0.7) for wires with width b/w 15 to 9999.
AREA 1.92 ; => min area for M1 is 1.92um^2
//res/cap/edge cap values below used to be there, but moved to cap table now.
RESISTANCE RPERSQ 0.066 ; => res is 0.06ohm/sq (sq=W/L)
CAPACITANCE CPERSQDIST 0.1 ; => cap is 0.1pf per sq um
EDGECAPACITANCE 0.1 ;
END MET1
--via1 layer --
LAYER VIA1
TYPE CUT ; => It's a cut layer and not routing layer
SPACING 0.8 ; => min spacing b/w vias is 0.7um
END VIA1
--similarly for MET2, VIA2, MET3 --
--Vias--
-- via defined here is as such: met1 is rect of (1.2,0.8), via1 is square of (0.6,0.6), met2 is rect of (0.8,1.0). met1 and met2 are not symmetric, since met1 runs horizontal with min width=0.6um while met2 runs vertical with min width=0.8um.
VIA VIAS12 DEFAULT
LAYER MET1 ;
RECT -0.600 -0.400 0.600 0.400 ;
LAYER VIA1 ;
RECT -0.300 -0.300 0.300 0.300 ;
LAYER MET2 ;
RECT -0.400 -0.500 0.400 0.500 ;
END VIAS12
--similarly for VIAS12A/B/AB, VIAS23, VIAS12DCN/E/S/W (double cut vias with orientation North,East,South,West), VIAS23DCN/E/S/W --
--top of stack via --
VIA VIAS23T DEFAULT TOPOFSTACKONLY
LAYER MET2 ;
RECT -0.700 -0.700 0.700 0.700 ;
LAYER VIA2 ;
RECT -0.400 -0.400 0.400 0.400 ;
LAYER MET3 ;
RECT -0.600 -0.400 0.600 0.400 ;
END VIAS23T
--viarule -- These specify rules for multiple via generation as in power rings.
#It describes a formula for generating via cuts using DIRECTION. If you specify DIRECTION, the WIDTH range is based on the connecting horizontal or vertical wire, not the layer of the connecting wire. Therefore, a horizontal wire that is between 0.6 and 14.9 units wide and a vertical wire that is between 0.8 and 14.9 units wide will trigger ViaGen12, independent of whether the horizontal wire is M1 or M2. It will create vias of 0.6x0.6 with an overhang of 0.3 on all sides and spacing of 1.4 on all sides b/w adjacent vias
VIARULE VIAGEN12 GENERATE
LAYER MET1 ;
DIRECTION HORIZONTAL ;
WIDTH 0.6 TO 14.9 ;
OVERHANG 0.3 ;
LAYER MET2 ;
DIRECTION VERTICAL ;
WIDTH 0.8 TO 14.9 ;
OVERHANG 0.3 ;
LAYER VIA1 ;
RECT -0.3 -0.3 0.3 0.3 ;
SPACING 1.4 BY 1.4 ;
END VIAGEN12
--similarly for viagen23--
--spacing--
SPACING
SAMENET VIA1 VIA1 0.800 ;
SAMENET VIA1 VIA2 0 STACK ;
SAMENET VIA2 VIA2 0.900 ;
END SPACING
END LIBRARY
-----------------------------------------------
TI core lef file: pml30_lbc8_core_2pin.lef
It has PnR info for all stdcells.
--initial info same as that for tech file, i.e version, units,etc--
#SITE => defines smallest size cell (1.7um is the pitch). It has cell height defined for CORESITE. All rows are in CORESITE (in the .def file), so PnR tool understands that it has to route VDD/VSS every 13.6um.
SITE CORESITE
SYMMETRY Y ;
CLASS CORE ;
SIZE 1.7 BY 13.600 ;
END CORESITE
#MACRO for all stdcells.
MACRO IV110 => inv x1
CLASS CORE ;
FOREIGN IV110 0.000 0.000 ;
SIZE 5.100 BY 13.600 ; => size 3 pitch wide.
ORIGIN 0.0 0.0 ;
SYMMETRY X Y ;
SITE CORESITE ;
PIN A => i/p pin A. i/p pins are all in Met1
DIRECTION INPUT ;
USE SIGNAL ;
PORT => pin shape in metal1
LAYER MET1 ;
RECT 1.300 5.800 3.100 6.800 ;
RECT 1.300 5.800 2.100 7.400 ;
END
ANTENNAGATEAREA 2.580 ; => antenna gate area to use for antenna ratio (AR) calc
END A
PIN Y => o/p pin Y. o/p pins are all in Met1, except for few complex cells, where it's in Met2, but internally routing is still all in Met1
DIRECTION OUTPUT ;
USE SIGNAL ;
PORT
LAYER MET1 ;
RECT 3.000 8.100 4.700 9.100 ;
RECT 3.000 7.900 4.600 9.100 ;
RECT 3.800 2.800 4.600 9.100 ;
RECT 3.700 2.800 4.700 3.800 ;
END
ANTENNADIFFAREA 1 ; => o/p pin is always connected to diffusion area, so specifies diff area to use for AR calc
END Y
PIN VSS => gnd pin VSS
DIRECTION INOUT ;
USE GROUND ;
SHAPE ABUTMENT ;
PORT
LAYER MET1 ;
RECT 0.000 -1.900 5.100 1.900 ;
RECT 0.700 -1.900 1.700 3.500 ;
END
END VSS
PIN VDD => pwr pin VDD
DIRECTION INOUT ;
USE POWER ;
SHAPE ABUTMENT ;
PORT
LAYER MET1 ;
RECT 0.000 11.700 5.100 15.500 ;
RECT 0.700 10.200 1.700 15.500 ;
END
END VDD
OBS => metal1 obstruction layer, we only have obs in met1 as stdcells only use Met1 internally to connect.
LAYER MET1 ;
RECT 13.400 4.000 14.200 8.300 ;
RECT 16.000 6.200 16.800 8.300 ;
END
END IV110
--similarly for all other stdcells--
END LIBRARY
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