Non SDC - lib data

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Last Updated: Thursday, 01 June 2023 23:12
Published: Thursday, 01 June 2023 20:05
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Non SDC - extracting lib data

Many times, we want to extract info for std cells from the library (.lib liberty files), such as power consumption, delay for certain FanOut, etc. It's not always feasible to get this from design data, as design may not have the cell we are looking for, or the Fanout of the cell may be different than the Fanout we are interested in. In such cases, we have to instantiate our own dummy design in the current design, and then run SDC or Non SDC cmds to get the required info.

We should use Synthesis tools to get info from library, as it's easy to instantiate our dummy design into the current design. Timing tools, such as PT are not really meant to modify an existing netlist, so they are restricted in how much they allow you to modify the netlist. Most of the times, it's easy to directly modify the netlist and insert your dummy logic in there, but over here, we'll modify the netlist using ECO cmds (For ECO cmds, see in ECO - Engineering Change Order section)

Sample Dummy circuit

Ex: Let's say we want to test the delay for a Fanout of 4 for an inverter in a given library. We should first create such an inverter cell, connect it to port on input and output, and then use a driver on i/p and load on o/p. Below are the steps for extracting lib data using various tools.

PrimeTime:

Create a dummy logic of an inverter where we first instantiate a dummy cell, then connect it to ports and then drive it appr and get timing.

  • Instantiate an inverter:
    • get_lib_cell *tsmc_n3*/INV_NOM_D1_*_SVT => shows INV_D1_NOM_SVT cell.
    • create_cell dummy_test [get_lib_cell *tsmc_n3*/INV_NOM_D1_NOM_SVT] => create an inverter with that std cell
    • get_pins -of [get_cells dummy_test] => This should show pins of Inverter (i.e IN and OUT)
    • get_att [get_pins dummy_test/IN] pin_capacitance_max => should show various attr present in .lib
  • Now create and connect nets on i/p and o/p pins, and then connect to new/existing ports.
    • create_net dummy_in; create_net dummy_out
    • connect_net [get_net dummy_in] [get_pin dummy_test/IN]; connect_net [get_net dummy_out] [get_pin dummy_test/OUT]
    • create_port -direction "out" {dummy_outp}; create_port -direction "in" {dummy_inp} => creation of new ports is not allowed in PT, so we need to use existing ports.
    • connect_net [get_net dummy_in] [get_port EXISTING_SPARE_PORT1] =>This won't work either as port already has a net with the port name, so it violates rule #2 of connect_net
    • disconnect_net -all [get_nets dummy_in]
    • connect_net [get_net -of [get_port EXISTING_SPARE_PORT1] [get_pin dummy_test/IN] => This connects pin to port
  • Now connect load on o/p pin and driver on i/p pin:
    • set load_fo4 [expr [get_att [get_pins dummy_test/I] pin_capacitance_max] * 4] => sets o/p load to 4X i/p load (so that gives FO=4)
    • set_load $load_fo4 [get_pins dummy_test/OUT] => Doesn't work as set_load cmd can only be used on ports and nets, and not on the pins directly.
    • set_load $load_fo4 [get_net dummy_out] => works as it's applied on net.
    • set_input_transition 100 [get_port EXISTING_SPARE_PORT1]  => instead of driving it with a driver cell, we instead directly control the transisition time
    • report_timing -thr dummy_test/OUT -tran -cap => reports delay of cell
    • get_attribute [get_timing_path -thr dummy_test/OUT ] arrival => This also reports delay, but now it can be automated in a script

DC: