SDC - all_* cmd

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Last Updated: Friday, 23 February 2024 08:30
Published: Thursday, 15 October 2020 05:26
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all_* cmds:

These all_* cmds return collection of objects of that type. Various options provide what attr we want for that object collection.

 


all_clocks => creates collection of all clcoks. No args for this cmd. ex: all_clocks => returns all clks in design

 


all_inputs => Creates a collection of all input ports.

ex: all_inputs -clock CLK1 => returns only those i/p ports that are clocked by CLK1

 


all_outputs => Creates a collection of all output ports.

ex: all_outputs -clock CLK1 => returns only those o/p ports that are clocked by CLK1

 


all_registers => Creates a collection of register (Flip flop or latches) cells or pins. This is very useful cmd to trace all flops/latches fired by a particular clk. Particularly helpful during clk tree debug, as it shows only the sink endpoints. The only endpoint that is missing from this collection is any output port connected to the clock. Lots of arguments possible.

syntax: all_registers <options>

options:

  • -clock <clk_name> => only returns reg clocked by given clk. We can provide only 1 clk name here as providing multiple clks will error out (SEL-006 Error). To see only flops or latches, use option <-edge_triggered | -level_sensitive>. For flops, we may also specify -rise_clock <clk_name> or -fall_clock <clk_name> to see only flops which are triggered by either rising or falling edge of given clk.
  • <-clock_pins | data_pins | -output_pins | -async_pins> By default, reg name shown (or use option -cells), but we can report corresponding pins of cells by specifying these options. -clock_pins option most useful.
  • <-no_hierarchy> => Considers only the current instance; does not descend the hierarchy. This is useful to isolate regs in different modules

ex: all_registers -clock CLK1 => -clock returns only those reg those are clocked by CLK1. Without -clock option, all regs shown (irrespective of whether they are clocked in design or not), but by adding -clock CLK1, only regs shown which are actively driven by CLK1 (i.e not disabled or tied off). This resulting collection can be passed thru foreach collection loop.

 


all_clocks => Creates a collection of all clocks in design. Fast and easy way to see all clks. No options supported. We generally use  get_clcoks cmd to get clocks. See in "clk cmd" section for details.

 

 

all_fanin => Creates a collection of pins, ports, or cells in the timing fanin of specified objects (pins, ports or cells), specified via -to. The fanin stops at the timing startpoints (clock pins of registers or PI). To see only the startpoint and not the whole path, we use option "-startpoints_only". Since most of the times we are not interested in the whole path, but just at startpoints, we use option "-startpoints_only".There are many other options as follows:

 

  • -from/-through can be used to restrict the fanin thru speciified pins, ports or cells.
  • -only_cells includes cells only (and not pins/ports) in timing fanin.
  • -flat should be used to traverse fanin across hier, else by default fanin doesn't cross hier.
  • -trace_arcs may be used to control what kind of combinational arcs to trace. By default (or -trace_arcs timing), only valid timing arcs are traversed (disabled arcs + invalid case analysis arcs not traversed) , but by using "-trace_arcs enabled", invalid case analysis paths are also traced (disabled arcs are still not traced). By using "-trace_arcs all", both disabled arcs as well as invalid case analysis paths are traced.
  • -levels allows us to stop traversal on reaching a depth of certain vells from the object in -to list. So, "-levels 1" will go only 1 level deep. This allows us to see paths one depth at a time.
  • -continue_trace generated_clock_source => This option is very useful for traversing clock network paths, as it allows tracing thru the source pin of generated clocks, instead of stoppping at seq pin of gen clk source. In most cases, you will want to use this option.
    • IMP: For a clk gater cell, the generated clk is sometimes defined at o/p pin or clk pin of clk gater. This is done in cases where we want the generated clk to be defined as async to the parent clk (as an example, bist clks are defined on the ck gaters, and then bist clks declared async to func clk). In such cases, all_fanin will stop at generated clk pin, as that's a timing startpoint. If we define generated clk on Q pin, and do all_fanin, then fanin will stop at Q pin. There will be no fanin from Q to CP pin, unless we use this option (or we define gen clk on CP pin).

ex: all_fanin -flat -startpoints_only -to mod1/..reg_2/D => shows startpoints only (not whole path) of all fanin to the D pin of this reg. Startpoints may be PI or clk pin of other flops or Q pin of clkgaters.

 

report_transitive_fanin => This is a reporting cmd, but is included here since it's very similar to all_fanin. Produces report showing transitive fanin (not timing fanins in all_fanin) of specified objects (pins, ports or nets), specified via -to. We can provide -from/-through to constrain the fanin. A pin is considered to be in the transitive fanin of an object if there is a timing path through combinational logic from the pin to that object. So, not sure how it's different than timing fanin of all_fanin cmd. We can use -trace_arcs option as in all_fanin cmd. The fanin stops at the clock pins of registers or PI. Fanin is provided within the current instance, so if we want to see all fanin, current instance should be set to top module. NOTE: this is reporting cmd, so can't be used in scripts (as it doesn't o/p a collection)

ex: report_transitive_fanin -to FF1/D => Shows driver of i/ pin of flop (FF1/D pin), then the driver of i/p pins of this driver and so on until it gets to PI or clock pins of reg.

 

 

all_fanout => same as all_fanin except that it reports objects in timing fanout. Here, -from specifies objects whose fanout we want (for fanin, we used -to). The fanout stops at timing endpoint (D or other i/p pin of registers or PO). Again option "-endpoints_only" may be used to report only endpoints, instead of the whole path. There's -clock_tree option to constrain the search to objects in clock network only (-clock_tree and -from are exclusive, only one of them can be used). All other options are the same as all_fanin.

ex: all_fanout -flat  -endpoints -from mod1/..or2/Y => shows endpoints only for all fanout from Y pin of this OR gate.

report_transitive_fanout =>this is similar to report_transitive_fanin, except that it gives fanout report. However, there is an addition option "-clock_tree" as in all_fanout.

ex: report_transitive_fanout -from FF1/Q => Shows load of o/p pin of flop, then the driver pin of that load, and the load connected to that pin and so on.

 

 

all_connected => Creates a collection of objects connected to a speciifed net, pin, or port object, or a collection of exactly 1 net, pin or port object. -leaf option when used with a net returns global or leaf pins. This very useful to see all the objects connected to a given net, and then trace thru a given path.

ex: all_connected [get_nets CLOCK] => shows all objects connected to net "CLOCK"

Get all connected pins of a net: There are 2 ways: 1 shown under "PT - object access functions" section. That uses "get_pins -of_objects ... -leaf" and the other is  "all_connected ... -leaf".

  • ex: all_connected  mod1/IO_port6 -leaf => Here it shows all leaf pins of gates connected to this port of module (ports of modules are actually pins, since ports are only for top level)
    {"mod2/GATE_and2_0/ZN", "mod1/mod3/I_OR3/A", "mod4/I_DFF/CP"}

 

 

NOTE: Above 3 cmds along with report_transitive_fanin/report_transitive_fanout are used to debug and trace timing paths, when we want to see the logic structure. We can see logic structure by bringing up gate level schematic of the netlist in any other tool (such as Verdi), but advantage here is that it has the ability to show only valid timing paths after accounting for inactive case_analysis and disabled timing arcs. This helps to find out where case_analysis may not have been set correctly, or why some timing path abruptly ends.