Clock Gating

Details

Last Updated: Tuesday, 30 July 2024 18:46

Published: Tuesday, 30 July 2024 17:04

Hits: 213

Clock Gating

Clock Gating is a technique to reduce power on chip. We talked about 2 techniques for reducing power:

• Clock Gating: This is where we turn clks on/off on different sections of chip as needed. This is what we are going to discuss in this section
• Power Gating: This is where we turn power  on/off on different sections of chip as needed. Here we get more power saving compared to clock gating as the whole power is turned off. This is implemented via sleep transistors or switches.

History of Clock gating

Most of the flops in design are not actively switching every cycle. By that I mean, data doesn't need to be updated all the times. Data from the driving flops may still get updated, but we don't want data being captured to be updated. There would be some control signal in RTL that achieves this functionlity. In the past, we would have a mux on the capturing flop that would select between new data coming in or recirculating the old dsts on the capturing flop. This could also be called as data gating, as we are gating the data so as not to toggle. This was correct in terms of functionality, but the clk was needlessly toggling on the capture flop. To save even more power, we somehow tie the control signal into the capturing clk. Then the capturing clk doesn't toggle, and hence data is held in the flop to previous value. This eliminates the mux. This results in power saving compared to the mux scheme. This is called clk gating and is used widely and supported by all synthesis tools automatically (you don't have to write RTL for clk gating, it's automatically put in by synthesis tools). The logic structure that we put in the clk path to achieve this is called a clk gater.

Clock Gaters

Clk gaters are special logic cells used to implement clk gating. So, how do we implement clk gaters? Very simple, we just turn clk on or off, so a simple AND or OR gate would do. AND gate is needed when clk is active high, while OR gate is needed for active low clks. However, there is a setup and hold requirement for this "ENABLE" signal, so that the clk pulse is not shortened or glitchy.

FIXME: Digram B-1

From the diagram, we identify 4 cases. In all 4 cases, setup/hold timing need to be met. See all 4 cases below:

Out of the 4 cases, simple AND/OR doesn't work for 2 cases. For those 2 cases, we need to have a latch before the AND/OR gate.

Testability:

Clk gater need to be testable, as they block clk during fucnc mode. So, during scan mode, they can block clk, depending on "EN" signal being 0 or 1.