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Published: Thursday, 29 September 2022 22:55
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Logic Analyzer:
I've included this since Logic analyzers and Oscilloscope are two very important equipment used to debug signals on a chip. Here's brief intro:
https://www.baldengineer.com/logic-analyzer-tutorial-introduction.html
In short, Logic analyzers look at a digital bus (multiple bits of data), all bits, at same time and samples them continuously for specified time. It's different from oscilloscope in teh sense that oscilloscope looks at the waveform of signal, and plots it in analog domain (in reality, it's digital as there's a analog to digital converter in digital oscilloscope. But the granularity is so fine, that it looks like an analog signal). But logic analyzer plots digital signals ((0 or 1 only), and shows the waveform on the analyzer. Logic means digital, so logic analyzer is analyzing digital signals.
Digital signals from inside the chip are brought on to some GPIO (General purpose IO) pins on the chip, and we connect these GPIO pins to the analyzer. We also have a trigger signal, that we can set to start the process of capturing these digital signals. These digital signals need not be from a bus, they can be unrelated to each other. Logic analyzers allow us to see all these signals at same time, and their timing relationship with each other. We are limited by the number of GPIO pins we have available on chip, which could be used for driving these logic signals. These Logic analyzers are able to sample in Megahertz rate, i.e 100 Million samples per second is now common.
On Chip Logic Analyzer (OCLA):
These are an extension of Logic analyzers where the whole logic analyzer sits on chip, instead of being outside off chip. Nowadays chips are complex and have very few GPIO pins in comparison to the number of signals that we may want to observe. Also, chips are running internally in 100's of MHz speed, and our off chip analyzer may not be able to capture signals that fast. To resolve all of these issues, we build OCLA as follows:
- Sets of signals that we want sampled are passed on to a memory on chip (along with some glue logic).
- There's a trigger signal that can be set based on desired conditions. Whenever the trigger signal is set, these probe signals start getting sampled and written to a memory on chip. These get written to the memory until that memory is full or some other pre set condition is met. The number of signals and the time period over which these are captured is limited by the memory size. So, trace of 128 samples for 64 bits of signals would require a memory size of 128*64=1KB of memory.
- We can get the contents of memory out using JTAG pins (via TAP on the chip). This doesn't disrupt the normal operation of the chip.
- We still need an offchip debugger (basically a software) that has gui interface that allows you to configure the ocla. We choose signals we want traced, setup a trigger and start the tracer. Once the trace is complete, the software will extract data from memory on chip (usually using JTAG pins) and generate a vcd file (vcd file is waveform viewer file, see in digital section). This vcd file can be loaded on to any waveform viewer to see the waveform. This vcd has the exact trace that the hardware was seeing, so it's exact replica of what was happening on the chip.
OCLA is very popular on modern SOC chips which have billions of transistors on them, and bugs are not easy to trace. Multiple OCLA on chip allow all kind of signals to be traced, without interrupting the device. Thus we can narrow down the location of bug, by viewing these waveforms and comparing them to a simulation run.
Here's a little intro on OCLA: https://www.electronicproducts.com/on-chip-logic-analysis/
OCLA interface:
can drive them on whichever GPIO pins they were assigned to.
