Memory Testing

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Last Updated: Tuesday, 04 April 2023 18:28
Published: Tuesday, 04 April 2023 17:33
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Memory Testing:

We learned in previous section on VLSI that all logic gates on silicon are tested via DFT (Design for Testability). Same would apply to sram memory on silicon too.Here we are talking about 6T SRAM meory, but the memory testing has to be applied to all kinds of memories inclusinfg DRAM, NAND, etc. We are limiting to to SRAM meories since these are the memories that are found on 99% of the chips as CPU, GPU, embedded chips and other digital/analog chips.

However memory can't be tested in traditional way of testing other gates. Reason is there are tons of memory bits (i.e there are 1M memory cells for 1Mbit mem). If we test each bit for stuck at 0 and stuck at 1, it will take a long time. First, we've to apply the addr to choose the intended bit, then write a 0, and then read out a 0. Then we write a 1, and read out a 1. Then we move to the next addr, until all the addr are exhausted. But we are not done here. Memory bits being in close proximity to each other have effect on each other, where writing a 0 or 1 in one bit, may perturb the value of other bit. So, we have to test all other bits when we have written a 0 or 1 to a single bit. And repeat this process million times for million bits. Assuming clk running at 1GHz, and memory of 1 Mbit, and rd/wrt time of 1 cycle only, reading 1M bits would need = 1M/1G=0.001sec. Now we repeat it million times, implying total time of 0.001sec*1M=1000sec. This is impractical and cost prohibitive.

BIST (Built in Self Test)

So, memory folks over the years observed the failing pattern of memories on silicon, and figured out what kind of interactions occur among different bits, and what kinds of patterns are going to give you the highest failure rate. Not all patterns need to be applied exhaustively. On top of that, instead of having a software program read/write memories, they built in hardware support for testing memories. Here in comes the BIST. It involved adding a state machine which would go thru all addresses of memories, rd/wrt appr values, compare the read values to expected values, and then generate a signature at end. Different kind of memory testing algorithms popped up. The most popular among them is 14N MARCH algorithm.

Memory Repair:

Since memory bits are placed very densely together, and are relatively less stable than logic cells across PVT (process, voltage and temperature), they are more likely to have failures. If we have to throw away the whole chip because of some defect in one of the memory bits, that would be pretty costly. So, redundancy was added in the memories, where few failing rows or columns may be swapped with spare rows and columns. These spare rows/columns were added to same meory array, but were just marked unused. When a failure was detected by the BIST engine above, these rows/columns would be swapped automatically by the BIST repair engine, and locked via some "fuse" bits, so that the next time chip powered up, it would be using the swapped rows/columns for failing bits. This was all transparent to the user, as everything was handled by hardware internally.

This memory test and repair is usually done everytime the chip powers up.

Diagram:

This is simplistic diagram of how memory logic looks like in presence of BIST.

CAD Tools:

In the past, BIST hardware was designed individually by each company to be used on their chips, since they had their own custom memories. Now, with memory compilers available from major CAD vendors, there's no need for designing your own custom memories. These CAD vendors alos supply BIST solutions to go along with their memories, so no need to code your own bist engine.

Synopsys Star Builder also knows as SMS (Star Memory System):

Star Builder is a tool by Synopsys which can add "test and repair logic" at RTL level to memories in your design. STAR stand for "Self Test And Repair". They also include the whole set of suites to verify the design at RTL level as well as diagnose memory in silicon, once these are added to design. In order for their SMS to work with other 3rd party memories, Synopsys developed a memory description language called MASIS. Using MASIS, you may specify your memory view, which will be used by SMS to integrate STAR logic in your design. MASIS is very simple text file, which specifies a "tag" for all i/p and o/p ports as Clock, Data, TestData, Address, TestAddress, ReadEnable, TestReadEnable, WriteEnable,, TestWriteEnable, BistEn, etc. It also has additional strutural details about rows, columns, etc. As per synopsys , SMS works better with Synopsys compiled memories, since then they can integrate the critical SMS logic within the hard memory macro allowing for better timing and area. SMS can be used with SRAM, DRAM, NAND or any other embedded or custom memory.

Star Builder has a GUI which has options to customize adding BIST. Or you may also use the command line tool called "buildersh" which is a Star Builder Shell to automate the process via scripts. SMS is added to RTL in multiple separate steps as shown below:

Here's a link for various steps: https://www.synopsys.com/dw/doc.php/memoriesandlogiclibraries/doc/latest/apnt0256.pdf

  1. Add memory wrappers around all memories in RTL design. These wrappers add extra ports for BIST purpose, and add muxes so that original functional operation of memories is not affected. For 3rd party memories, MASIS view has to be provided, so that tool can figure out where to place bist test ports.
  2. Now add SMS processor (or state machine) that will control these BIST ports on memories. You may configure to have one SMS processor for each memory or group multiple memories under one SMS processor.
  3. Once these SMS processors and memory wrappers have been added at block level, we can now have a master SMS server that connects to all these SMS processors for each block, and communicate to them via IEEE1500 protocol. We can have an optional TAP logic at top chip level, that can communicate with this SMS server and initiate STAR tests for memories when needed. We usually also have an interface on the SMS server for software to write into it's registers which will allow software to control BIST and repair too.

Once SMS is added, we can verify new RTL by inbuilt tests provided. Once silicon data is available, the yield Accelerator tool can analyze memory failures and provide guidance for yield improvement.