JTAG

Details

Last Updated: Monday, 09 December 2024 19:32

Published: Monday, 03 October 2022 22:56

Hits: 646

JTAG:

If you've ever been involved in debug of a chip, you must have heard of JTAG. in 1980's, boundary scan was developed along with Test Access Port (TAP) to get access to internals of the chip using just few test pins on the chip. This scheme was standardized in IEEE 1149.1, which came to be known as JTAG. JTAG or Joint Test Action Group is the name of the group which developed it, but the term JTAG was given to this std too.  Here are few links to JTAG intro:

Introduction to JTAG and TAP: https://www.allaboutcircuits.com/technical-articles/introduction-to-jtag-test-access-port-tap/

JTAG connectors and i/f: https://www.allaboutcircuits.com/technical-articles/jtag-connectors-and-interfaces/

All JTAG compliant devices have these blocks:

1. Test Access Port (TAP): This is additional pieceof logic that is added on the chip. It has 4 or 5 standard pins thru which we get access to data inside the chip, as well as drive data to write into the chip to make it perform some action. We'll have a separate section on TAP. Here's some intro: https://www.allaboutcircuits.com/technical-articles/jtag-test-access-port-tap-state-machine/
2. Boundary Scan Registers (BSR): The std allows for implementation of Boujndary scan. Recall that chips now have 1000's of pins on the package, and it may not be functionally possible to drive all the pins of the chip to desired values. Boundary scan std solves this issue. In testmode, it allows user data to be driven on these IO pins. That way we can control all values on IO i/f of chip. This is very helpful in debug of other chips connected to this chip. We can also read values that are driven on input pins of our chip.

Together TAP and BSR constitute JTAG std.

SWD:

ARM's Serial Wire Debug (SWD) is an extension of JTAG developed by ARM Company. This is brief intro about ARM's SWD.

ARM SWD: https://www.allaboutcircuits.com/technical-articles/jtag-implementation-arm-core-devices

Interface Timing:

Both Jtag and SWD i/f have 1 common timing protocol they adhere to => Data is always captured (by the slave or target) on rising edge of clock. This means that Data should be driven by the driver (master or host) on the falling edge of clock, so that we have 1/2 cycle setup and 1/2 cycle hold. However, this is not compulsory. Master can drive data on rising edge of clk and slave can still capture the data on next rising edge of clk, iving a full 1 cycle setup. But in this case, the hold time is 0 cycle, which may be difficult to meet across all corners.

JTAG Timing diagram:

ARM's SWD Timing diagram:

ARM link => https://developer.arm.com/documentation/dui0517/a/serial-wire-debug/swd-timing-requirements?lang=en