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Published: Wednesday, 03 January 2024 18:23
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RDC = Reset Domain Crossing

RDC is reset domain crossing. For a given reset signal, the logic being initialized by it, is defined as a reset domain. Just like clocks in CDC, reset signals crossing reset domains can be an issue if not done right. A problem can occur at the interface of 2 reset domains (same clock domain) when one is being reset while the other is not. These are some of the issues to be careful about when dealing with reset signal.

  1. Reset Synchronization: Just like CDC, RDC can be an issue when reset signal crosses clock domain. Reset signal needs to be synchronized properly across clock domains. This is irrespective of whether reset signal is going into D pin of flops or async set/reset pin of flops. In this case, reset signal is just like any other signal crossing clk domain, and hence needs to eb synchronized before being used. This is checked as part of CDC, and NOT RDC.
  2. Glitch free Reset: Just like Clock signal, reset signal should be clean, i.e no glitches. Else, flops may get incorrectly reset.
  3. Sync vs Async  Reset: We have 2 styles of reset methodology in design:
    1. Synchronous Reset => Sync set/reset flops have reset coming into D pin of flop, which makes reset similar to any other signal (nothing special to reset). This makes RDC checks very easy. In this methodology, at the reset port, we have a synchronizer that asserts and de-asserts reset synchronously. Using Sync Rest is the preferred design methodology for all designs. It is however not always possible to use a full sync reset methodology. Below are few cases, where we have to use Async reset methodology:
      • Clock is not guaranteed to be running when the reset is asserted. In such cases, reset can't pass thru the flop and rest the design, until clock comes, which may be too late.
      • When logic needs to be reset right upon reset assertion, then we need Async reset. Ex are IOs, PHYs, test logic, etc.
    2. Asynchronous Reset => Async set/reset flops have reset signal going into Async pin of flops. In this methodology, at the reset port, we have a synchronizer that asserts reset asynchronously, but de-asserts synchronously. So, de-assertion of reset is NOT an issue, but assertion is. Further, this reset signal goes to async set/reset pins of flops (instead of going to D pin of flops). STA tools do recovery/removal checks on these paths, making sure they don't violate setup/hold time wrt clock. But they don't time the path thru the Async pin going to output pin of flop, and then going into the D pin of next flop. This path may violate setup/hold time of next flop asit is async to other domain, and cause metastability. If all these flops are in the same reset domain, then it's not an issue, as all flops get reset assertion, so all flops are anyway going to be reset. However, if the destination flop is in a different reset domain, which is not being reset, then the metastability issue may cause the destination flop to have unknown value for a cycle, which may propagate to other flops. So, the main issue with Async reset methodology is due to STA tools not timing the path from Async set/reset pin to Q pin of the flop (reset assertion), resulting in metastability. RDC primarily catches all these issues. For designs where we have to use Async reset methodology, we should stick with following guideline:
      1. Only POR reset (power on reset) should be connected to async set/reset pin of flops. Using other software or functional resets exposes the design to potential RDC issues.
    3. Hybrid Reset => This is reset methodology where we mix sync and async reset methodology. In this case, we should have Reset port go thru 2 synchronizers in parallel, one for sync reset (both assertion and de-assertion is sync), and another for async reset (assertion is async, but de-assertion is sync). Sync reset flops are driven by sync reset synchronizer, while Async reset flops are driven by Async reset synchronizer. This keeps the 2 methodolies separate, and much less RDC issues across the two.

 

 

RDC Fixes:

 

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Published: Wednesday, 27 December 2023 08:11
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Verbs:

Verbs can be in different forms, different tenses, different moods. They can be main verb or auxillary verb, be in active voice or passive voice, etc. Thus it's hard to group verbs in just one tree branching out, as tenses, forms, voice, etc overlap with each other. Usually we know verbs by their tenses, i.e whether it's in past, present or future. However, keep in mind that tenses are just one classification style of verbs, there are other classifications too.

Link: https://espanol.lingolia.com/en/grammar/verbs

 

Verb forms:

English: In English, there are only 5 forms of verb as shown below. Forms means different transformation of the verb. For ex: run can have diff forms as run, ran, running, runs, etc. These are all different forms. Of these 5 forms, first 3 forms are most commonly learnt when learning => These are past/present/past_participle forms of verb.

Link: https://www.careerpower.in/verb-forms.html

  1. Present (Root) form of a verb (V1) => This is the base form of verb w/o modification. i.e I run. Here verb "run" is base form of verb.
  2. Simple Past form of a verb (V2) => This denotes action done in past, i.e I walked. These are formed by adding -ed/-d to end of base verb for regular verbs. For irregular verbs, no simple rules (i.e I ran)
  3. Past Participle form of a verb (V3) => This form of verb is similar to simple past form (V2), but always come with an auxiliary verb. Ex: "He played" vs "He had played". "He played" is simple past or V2 form, but "He had played" is V3 form. It needed auxillary verb "had". Past participle is refered as "past" since the verb form is of "simple past" with -ed/-d added. Sometimes, it's with -n added too (i.e took vs taken). However it doesn't mean event had already occurred. It can be used in past, present or future tense. Ex: He had been called, he is being called, he will be called => all 3 are V3 form and verb is in past form, but with the correct auxillary verb, it can represent all 3 tenses.
  4. Present Participle form of verb (V4) => This form is created by adding -ing to the base form. It’s used in the past, present, and future progressive verb tenses. Ex: He was running, he is running, he will be running => all 3 are V4 form, but in 3 diff tenses.
  5. Third -person singular Present form (V5) => This is the V1 verb, but instead this is used for 3rd person, i.e He, she, it, etc. It is denoted by addition of -s or-es to the base form, i.e he plays badminton. Here plays is V5 form.

Spanish: All Verbs in Spanish are of 2 forms - Personal and Impersonal. We choose which form to use depending on how the verb is to be used with the subject. We don't have 5 forms as in English. This will become clear later with examples.

Link: https://espanol.lingolia.com/en/grammar/verbs

  • Personal form: These are verbs which change according to nouns/pronouns attached with the verb (i.e I run). They follow the same 3x2 table as shown for pronouns in previous section -i.e whether nouns/pronouns are 1st, 2nd , 3rd person (nouns are treated as 3rd person) and whether they are singular/plural. (Same as 3x2 pronoun table shown). So, we have a 3x2 table with 6 versions of these verbs. These are called personal form as verb changes based on person and number. In English, I eat and you eat, both use same verb "eat", but in Spanish, "eat" changes based on "I eat" vs "you eat". In English, we sometimes do that with specific verbs => an ex is verb "run", as in "I run" vs "he runs". In Spanish, it happens with almost all the verbs. This is called Conjugation, where verbs change their endings to reflect the subject of the sentence in person and number. Since the verb form indirectly specifies the subject pronoun, we omit the pronoun all together for 1st and 2nd person (i.e instead of saying "I eat banana" or "yo como plátano" we just say "eat banana" or "como plátano" as verb "cpmo" (from base word comer)  implies "I eat"). We'll see these in ex below.
    • ex: I eat => como (base verb is comer, but is transformed based on pronoun "I")
  • Impersonal form: These are verbs which don't change based on noun/pronoun attached to the verb. So, they are called impersonal, as they don't depend on person. No complicated 3x2 table to memorize, as all forms are same. There are 3 forms of these verbs:
    1. Infinitive form: Every verb can be put in Infinitve form, where the verb remains in it's base form (i.e walk). This is same as V1 form in English, and is also the  simple present tense of the verb. The word "to" added in front of the verb doesn't change the base form of verb. So, "to walk" is also an infinitve form of verb. In Spanish, infinitive form of verb is with the word "to" in front of it. All verb infinitives end in -ar, -er or -ir.. These are base verbs, and all verbs are formed from one of these base verbs.The base word implies "to do something". ex: hablar which is an ar verb means "to speak". If we just say speak, then it's not hablar, but is transformed based on the noun doing the verb. So, this verb is converted to personal form that we read above.
      • ex: cantar => to sing
    2. Gerund form: The gerund of Spanish verbs is equivalent to the English -ing form. Explained under "gerund" section.
      • ex: cantar (to sing) => I am singing => estoy cantando
    3. Participle form: The participle is equivalent to the English past participle (V3 or third form of the verb). Explained under "participle" section.
      • ex: cantar (to sing) => I have sung => he cantado (NOTE: gerund form was cantando, while here it's cantado

NOTE:

  • Gender: Verbs do NOT have a gender. So, no matter the gender of noun, verb remains the same. But verbs change according to forms discussed above. For personal forms, it's 2X3 table. Each verb can exist in various tenses, and each tense has it's own 3x2 table. We'll discuss tenses below.
  • Endings: Verbs in Spanish always end in -ar, -er and -ir. Whenever you see a Spanish word with these endings, remember they will be verbs. In English, we can't look at a word, and say it's a verb (i.e "speak" - you can never figure out it's a verb, based on it's spelling, but in spanish, it's "hablar", and as soon as you see -ar, you know it's a verb).
  • Consecutive verbs: When we have 2 verbs back to back, how do we conjugate them. Do we conjugate both of them based on the subject or just one. Well, conjugating both verbs will sound weird and also unnecessary since conjugation of 1 verb will be enough to indicate who the subject is. We usually conjugate the 1st verb, and have the 2nd verb in infinitive or participle form. We saw in "Participle form" above that "I have sung", "have" is the one that's modified as per 3x2 table.

 

Verb Moods and Tenses:

In Spanish, verbs also have moods - Moods help specify the speaker’s intention. In Spanish, there are three verb moods: With each mood, we have certain tenses. Tenses are same as in English - past, present, past progressive, future tense, etc. There are 18 Spanish verb tenses. Link: https://blog.rosettastone.com/your-complete-guide-to-all-18-spanish-verb-tenses-with-examples/

Out of these 18 tenses,10 tenses go only with indicative, 6 go only with Subjunctive and 2 only with Imperative. Why do we talk about moods when talking about tenses? => Because, the verb conjugate differently depending on the mood. So, the same present tense will conjugate differently in 1 mood than the other mood. So, basically we have 18 conjugate tables that we have to learn for each verb. So, 6 entries for each conjugate table implies about 100 conjugations you have to remember for each verb. With 1000's of verbs, that's 100K of verb conjugations !! Fortunately, we can get away by learning just 3 conjugate tables for simple past, present and future.

We'll see the Moods and allowable tenses in each mood:

  1. Indicative mood (el indicativo): It is used for objective statements, events, actions and facts. It is the default mood and  expresses real information that is known or certain. Normal sentences are usually formed in the indicative mood. It's how we normally talk in English (Indicative mood). It is present in all tenses as present, past and future. There are not just 3, but 10 tenses that go with indicative mode:
    1. Present tense (Presente): This is simple present tense just like Present tense in English (V1 form in English)
      1. ex: He cleans the Kitchen => limpia la cocina. limpiar means "to clean". 3rd person form is limpia.
    2. Past tense (Preterit or Pretérito/Indefinido): This is the simple past tense (V2 form in English).
      1. They bought a new car => Compraron un coche nuevo.
    3. Future (Futuro Simple): This is the future tense in English as "I will do", etc.
      1.  I will talk to my father tonight.=> Hablaré con mi padre esta noche.
    4. Perfect form (Perfecto): Perfect tenses are participle form, i.e I had studied. All perfect tenses use the auxiliary verb haber (ex: had) along with a past participle main verb (studied). We saw the Participle form above, which was the V3 form in English. Along with past participle conjugate, we need "haber" verb conjugate to form sentences like "I have eaten", etc. The past participle of main verb (eaten) is formed by removing the ending of the infinitive and adding -ado for -AR verbs or -ido for -ER and -IR verbs (this was already explained above). The perfect tense of auxillary verb (have) is added to this to form the perfect form. Spanish translation of "have" is haber. Haber comes in all 3 perfect tenses as present, past and future, just as in English => I have, I had, I will have, are all possible by having the 3 tenses for haber. The haber table for all 3 tenses is in Verbs - ar,er,ir section. The main verb remains the same. We show the 3 Perfect forms => Present, Past and Future:
      1. Present Perfect (Presente Perfecto): He has eaten
      2. Past Perfect (Preterito Perfecto): He had eaten. One other form of this exists as shown below.
        1. Preterite Perfect (Preterito anterior): This tense is mostly used in formal speech or in literature, so no need to learn this. It describes an action in the past that happened immediately before another action in the past. ex: After we had eaten, he served dessert.
      3. Future Perfect (Futuro Perfecto): He will have studied.
    5. Past Imperfect (Preterito Imperfecto): You use this tense to talk about past actions generally, without a specific duration. Also commonly referred as "Imperfect tense" (instead of "past imperfect tense") as past is already implied. Ex: He used to play tennis. See in Past Imperfect section.
    6. Conditional (condicional simple): This is used to talk about hypothetical situations and make requests. Ex: We would take out the trash for you.
      1. Conditional Perfect (condicional perfecto): There is another form of conditional mood. It’s used to talk about actions that would have happened, but didn’t due to another event. You can also use it to talk about actions that probably happened or were likely true. Ex: He would have read the book, but his friends came. Not important to learn these.
  2. Subjunctive mood (el subjuntivo): It is used for expressing emotions, desires, and possibilities. It expresses hypothetical, vague or unverified information. It s called subjunctive as it indicates subjectivity of the fact. It is often used in subordinate clauses that follow a negative statement. Ex: I wish that it would rain today. One way to memorize what the subjunctive covers is to use the acronym WEIRDO:
    1. WEIRDO:
      1. Wishes
      2. Emotions
      3. Impersonal expressions
      4. Recommendations
      5. Doubts/denials
      6. Ojalá (“Hopefully/I wish”)
    2. Present (Presente de subjuntivo): ex: Lamento que tengan que irse. = I’m sorry that they have to leave.
    3. Imperfect (Imperfecto de subjuntivo): This s past tense of subjunctive mood. used to talk about feelings related to past events, as well as hypothetical situations. ex: I wanted you to come to my party.
    4. Future (Futuro de subjuntivo): This is rarely found in modern Spanish, and its uses are largely covered by the present subjunctive. ex: Wherever you go, do what you see.
    5. Perfect form (Perfecto): Similar to perfect tense in Indicative form, we have it here too. they use auxillary verb "haber" along with main verb. All 3 tenses of present, past and future are present here too.
      1. Present Perfect: It is similar to the present subjunctive, except that it covers past actions that are connected to the present, as well as actions that will have happened at a certain point in the future.
        • ex: My teacher doubts that I have read the book.
      2. Past Perfect: It to describe hypothetical situations in the past, conditional situations in the past, and past actions that preceded other actions.
        • ex: If I had known, I would have come.
      3. Future Perfect: Similar to Future Subjunctive, this form is rarely used.
        • ex: Priority will be given to those matters that fall under the emergency procedures provision.
  3. Imperative (imperativo): Similar to perfect tense in Indicative form. It is used for giving commands, making requests, giving advice, etc. addressed to one or more people directly. These verbs don't conjugate or change the same way as is done for personal verbs. The 3x2 table is still there, but it it has it's own table for -ar, -er and -ir verbs. We'll look at those in verbs - ar, er, ir section. They come in 2 forms:
    1. Affirmative Imperative: When we give a cmd to do something in affirmative. ex: Eat your food.
    2. Negative Imperative: When we give a cmd NOT to do something. ex: Do NOT go there.

Most common verbs:

There are 300 most common verbs that will cover 99% of verbs ever used in conversations. Some of them are irregular (see below), but knowing conjugation for even some of them will enhance your Spanish a lot.

Link to 100 most used verbs with Pics: https://www.youtube.com/watch?v=dhIQ2BfrxTM

 

 

Verb Conjugation:

We are going to look thru various spanish verbs in next few sub sections. Verbs in Spanish come in only 3 different endings => -ar, -er and -ir.

ex: pintar => to paint

There are few exception verbs which don't end in -ar, -er or -ir:

  • busara => to search. Other word basura means Trash, garbage (i.e the physical garbage that we pick up).

Some words end in -ar, -er or -ir, but are not Verbs:

  • amanecer => sunrise. atardecer => sunset. (both end in -er)

Verbs conjugate (i.e transform) based on the mood, tense, etc. There's a 3x2 table that helps us in making this transformation. This transformation table id different for different tenses, moods, etc.

Irregular verbs: These verbs are irregular, meaning they don't follow our usual 3x2 transformation table. These are discussed under their own section, as there are too many here. We need to learn some of the most commonly used irregular verbs. A lot of regular verbs turn out to be irregular in some conjugation table. But this will come with practice.

 

 

 

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Published: Tuesday, 19 December 2023 10:37
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VC (Verification compiler) Static Spyglass

This is the newer version of Spyglass (as of 2022) which is integrated under Synopsys VC platform. It has native SDC support, with DC/PT cmds supported in VC.

Running VC Spyglass (SG) standalone:

VC SPYGLASS is usually installed in a path like this: /project/tools/synopsys/.../ => We'll refer to this as "$VC_STATIC_HOME"

VC spyglass invoked by typing full path as $VC_STATIC_HOME/bin/vc_static_shell or "vc_static_shell" or "vc_static_shell -gui". The shell version (no gui) brings up "vc_static_shell" where we can enter spyglass cmds. "gui_start" on shell also brings up the gui. Tcl 8.7 is supported in sg_shell.

vc_ststaic_shell -f input.tcl => This runs VC spyglass with script provided. We provide all SG cmds as well as tcl cmds in input.tcl.

Inputs/Outputs to VC SG: VC static shell is used to take input cmds and generate output reports. Verdi is used to navigate RTL, view waveforms, etc, so it's lot comfortable for folks used to Verdi Gui.

  • Inputs: VC SG takes input as RTL/netlist and stdcell .lib files (if netlist provided, or if RTL contains stdcells instantiated, only then are .lib files needed). All inputs are provided in std tcl format.
    • Project file => .prj files are translated to tcl file in VC SG.
    • Constraints => .tcl file. These are std SDC constraints as well as additional non SDC cmds from DC/PT. New cmds related to reset also added. See next section.
    • Waiver files => object based tcl files. No more .awl/.swl waiver files.These are waivers that apply to Errors/warnings (ones that we want to waive)
  • Outputs: SG provides output reports.
    • Reports => .rpt files which list Lint/CDC/RDC violations.

 

 

VC SG CDC Script

Below is a sample CDC script to run the SG CDC tool. This file is divided in 3 sections => design constraint setup, cdc check and Analyze results.

First invoke the tool and then run the below script (setup.tcl).

  1. design constraints and settings:
    • Since VC SG supports al 3 checks (lint, CDC, RDC), we select which to enable
      • #set_app_var enable_lint true; ## enable lint
      • set_app_var enable_cdc true; ## enable cdc
      • #set_app_var enable_rdc true; ## enable rdc
      • set_app_var enable_resetless_analysis true #set cdc var for resetless analysis
    • ## read design
      • set_app_var search_path <directory_list>; ## define search order of source directories
      • set link_library <library_list> ; ## list db technology libraries
      • set_app_var vsi_dwroot <path_to_compiled_DW_library>
      • read_file -top test <list_of_source_files>; ## this cmd does both analyze and elaborate in single step. Or we can do in 2 steps:
        • analyze -format verilog <source_file_list> -vcs {-work WORK -sv=2005 -error=noMPD}
        • elaborate <top_module >; ## build and synthesize top design
    • ## configure cdc => This says how do we want to run the checker, i.e for CDC, do we want to check for synchronizers, input/output ports, etc.
      • configure_unconstrained_ports ……; ## clocks for unconstrained bbox ports
      • configure_cdc_nff_sync ……; ## control sync schemes
      • configure_cdc_data_sync ……; ## data sync schemes
      • configure_cdc_asyncrst_nff_sync ……; ## asynchronous reset control sync schemes
    • ## read cdc constraints. SDC cmd format shown later.
      • read_sdc common_constraints.sdc ; read_sdc cdc_constraints.sdc ; ## read multiple constraint file
  2. Run CDC checks
    • #check_lint => runs lint checks
    • #check_rdc => runs rdc checks
    • check_cdc -type setup|sync|struct. Run each one in separate step
      • check_cdc -type setup => Checks for proper clock, reset setup. All setup issues should be resolved before performing other cdc checks. It does following checks:
        • SDC: sanity checks SDC/Tcl constraints for CDC
        • CLKPROP: Propagates clocks and checks resulting clock structures for CDC
        • RESET: Propagates resets and checks resulting reset structures for CDC
      • check_cdc -type integ => Checks clock and reset integrity. Ensures that the clocks and resets are properly defined and are free of glitches, race conditions, and other hazards.
      • check_cdc -type sync => Checks for proper CDC path synchronization (control, data and async reset CDC paths).
        • The 3 configure_cdc_*_sync cmds in "settings" stage above set these cdc checks
      • check_cdc -type struct => Checks sync, correlation (or convergence) and glitch. It runs after CDC crossings have been identified.
  3. Report Results
    • #report_violations => This can be used to report viols for all 3 checks => lint, cdc and rdc. -app {cdc} or -app {rdc} or -app {lint} will report only for that check.
    • report_cdc => type -help to get options to use. Reports cdc viols only.
      • report_cdc -verbose -limit 0 -file viol.rpt => report all viols and dump into the file viol.rpt. -limit limits viols to be reported to that number. Without any options, report_cdc reports summary of all viols.
    • waive_cdc => type -help to get options to use. Options almost same as report_cdc above. -filter option used more often here to waive viols based on certain names. Never set waiver by tag ID (i.e -id). IDs change from run to run
      • waive_cdc -stage sync -tag SYNCCDC_UNSYNC_NOSCHEME -filter "SrcObject =~t1/Q && DstObject =~t2/Q"

Type "quit" to quit the tool

Hierarchical flow: Here we run CDc on each block, and then generate an abstract model for each block. That model contains all necessary CDC info, that can be used to identify CDC issues at top level, by just using the Abstracted model of blocks. This saves run time at top level for big designs, which have large blocks in them. We run CDC at top level, in similar way as at block level, except that block levels are not RTL anymore, but Abstract models.

 

 

SDC/non-SDC commands for use in CDC constraints:

 

  • SDC cmds => These are std SDC cmds. no difference in syntax.
    • create_clock / create_generated_clock => for creating clk and generated clks
      • create_clock -name VIRTUAL_CLOCK_0 -period 2.0 => This defines a clock with no ports assigned, implying it's a virtual clock with a period of 2ns, or freq=500MHz. This cmd is used very often in CDC/RDC flow to define virtual clks.
      • create_clock -name MY_CLK -period 2.0 CLK_PORT=>Here we define a real clk on one of the clk ports of the design
      • To automatically infer clks/reset, we can use the cmd: infer_setup -type [clock|reset] -[full|incremental] (use -help to get the syntax)
      • view_clock_tree -clock CLK1 => This is used to view clk tree for CLK1
    • set_clock_groups -async => define explicit async relation b/w clks
      • set_clock_group -asynchronous -group { VIRTUAL_CLOCK_0 } => Usually virtual clks are defined async to all other clks in design, including other virtual clks. The whole reason we created a virtual clk is so that we can assign that virtual clk to an i/p port, and treat that port signal as coming from an async clk source. CDC tool will then treat this port as being on an async boundary and do all CDC checks.
    • set_clock_sense => to disable clk propagation from specified pins
    • set_case_analysis / set_mode => defines constant values on pins/ports/nets. set_mode defines active mode of libcell inst (in case cells have multiple modes as scan, etc)
    • set_input_delay / set_output_delay => This defines port's relationship to clock, i.e port is driven/captured by which clk. This is very imp cmd, which is needed to determine if a synchronizer is needed on input ports. Ports can also be constrained via attribute cmds discussed later. That is the preferred approach.
      • ex: set_input_delay 1 -clock [get_clocks ck_2] [get_ports i_rst_2]
      • To automatically configure unconstrained ports, we can use the cmd: configure_unconstrained_ports (use -help to get the syntax)
  • Extended SDC cmds => These are non std SDC cmds. They were added in CDC tool, since we need to define certain things, which are not supported by std SDC cmds
    • create_reset => defines reset on pi/port/net object. This is being shown as SDC cmd in Synopsys manual (as of 2023), so it's an SDC cmd now.
    • set_reset_sense => similar to set_clock_sense, it is to disable reset propagation from specified pins
    • create_static => Defines static assumption on pin/port/net objects (this is when we have quasi-static values => values that don't actively change, but change only once in a while under user control. This means that we control when to change that value, and can afford to wait few cycles to propagate the correct value. This in turn implies that a synchronizer or other CDC checks are NOT needed, as correct value will eventually get propagated)
    • attribute cmds: These are attr (or path elements) which are attached to the design objects. They may be attached to different object classes as clock, port, pin, net, cell, design or any other real objects in design. attr are also called as "virtual objects/nodes" as they don't exist in design, but actually map to real objects. We attach these to ports/pins, etc and then start adding properties to these virtual nodes, which in turn apply to real ports/nets etc to which these attr are attched to. These attr are same as what we saw in attribte cmds in "Non SDC attribute section" of "vlsi digital std". However they seem confusing in how they are defined and used over here. First, when we try to report attr of any object, they don't show up in any object attr list. Also, when we try to report all attr in design, they don't show up either. Secondly they don't have any value attached to them. They are simply "exist" or "don't exist" attr.
      • define_attribute => creates a virtual path object. Once created, we can attach it to a real object, or may leave it unattached.
        • syntax: define_attribute -name <attribute name> -objects <pins_or_ports> => <attr_name> is the logical name of the virtual path object (i.e virtual node). We can either create this "virtual path object" w/o associating it to any real object in design, or may associate it via -objects. Many more options allowed. If -objects option is used, then apply_attribute cmd (defined below) is not allowed, as this cmd already applies the attr to the object.
      • apply_attribute => Once we defined an attr above, we can apply it to specific objects in design. This cmd specifies the pins to which the specified virtual nodes are applied. This is only needed when above "define_attribute" cmd is used w/o -objects option.
        • syntax: apply_attribute <attribute name> -objects {list of pins} => <attr_name> is the name of attribute element defined by define_attribute. Many more options allowed.
      • Misc set_*_attr => Many more attr cmds. All these cmds are of type set_*_attribute, where * refers to objects to which attr attach to, i.e clocks, reset, tag, etc. Or they may refer to extra property that is attached to that attr, i.e combo_att implies combo property is attached to that attr. -add option allows for adding this attr property on top of previous attr properties specified.
        • set_clock_attribute => This cmd specifies the attribute name to which the clk constraints is to be attached. Basically it specifies the clk which drives the given virtual node (which is the attr name). So, it's same as "apply_attribute" cmd above, except that it says the clk constraints are being added to this attr. 
          • syntax: set_clock_attribute <attribute name> -clocks <clk_names> -clock_objects {pin_names} => <attr_name> is the path element or name of attribute to which clk constraints are to be attached. -clocks specifies clk_names, while -clock_objects specifies clk ports. These are mutually exclusive, and only one of these may be used. Many more options allowed.
            • ex: define_attribute -name path1; set_clock_attribute path1 -clocks c1; apply_attribute path1 -objects {in1 in2}=> same attr path1 is applied to both clock (c1) and ports (in1 and in2).
        • set_reset_attribute => This is same as set_clock_att cmd above, except that it specifies the resets (reset name/pin) which drive the given virtual node. -combo defines a combo logic before the virtual sequential.
          • ex: define_attribute -name path1; set_reset_attribute path1 -reset_objects rst1 => Here rst1 pin drives the virtual node "path1". If path1 is attached to some ports, then those ports get driven by this reset pin too.
        • set_sync_attribute => Just like clock_attribute cmd above, here sync property is set on the virtual node which is being driven by synchronizers. We specify the synchronizers that drive the given virtual node in this cmd itself. 
          • syntax: set_sync_attribute <attribute name> -from <clk_names/pin_names> -to <clk_names/pin_names> -sync <active/inactive> -sync_names <list> =>-from/-to specify the synchronizer src/dest clks/pins. -sync active specifies that this synchronizer can synchronize other crossings also, while -inactive means it's meant for only one crossing. -sync_names specifies synchronizer names reaching the virtual node.
            • ex: set_sync_attribute async1 -sync active -to vclk1
        • set_connectivity_attribute => Specifies the type of connections between the pins of the blackbox instance.
        • set_tag_attribute => applies attr to violation tags. Name and value of attr to change is specified for the given tag.
        • set_test_attribute => applies dft related info to given attr. The attr is first attached to given pins/ports and then this cmd is used to attach dft info to those pins/ports. -testbus specifies that defined ports/pins are of type testbus, while -analog specifies they are of type analog.
        • set_ignore_attribute => This is used to ignore validation of the design objects on which this attribute is applied
        • set_combo_attribute => This cmd is used to attach combinational property to an output port. This helps CDC to analyze and report mismatches.
          • ex: apply_attribute path1 -objects in1 -direction input; set_combo_attribute path1 -value yes => applies combo prop to i/p port.
      • report_attribute =>This is the same cmd that is shown in "Non SDC attribute section" of "vlsi digital std". It reports attr on one or more objects.

 

Constraining ports via Attribute method: 

Ports can also be constrained via scope-attribute method (by using attribute cmds shown above) instead of set_input_delay. ex below:

  • set_constraints_scope -module BBOX2 => constraints below will only to this module BBOX2.
  • Constrain i/p Port DAT_1 with real clk => First we define clk on CLK port. Next define a clock attr and associate it with this virtual clk. Finally apply this clk attr to the i/p Data port. This implies that DAT_1 is being driven by clk on port CK_1. Similarly more ports can be constrained.
    • create_clock -name my_clock -period 2.0 -add CK_1 => create clk "my_clk" on clock port CK_1
    • set_clock_group -asynchronous -group { my_clock ... } -group { ... } => define async relations as needed
    • define_attribute -name myclk_attr => define attr
    • set_clock_attribute myclk_attr -clocks {my_clock} =>  apply attr to clk created above. So, it becomes clk attr now
      • #set_clock_attribute myclk_attr -clock_objects [get_ports CK_1]; => This is alternative way where we can specify clk attr directly on clk port CK_1. Not sure what's the difference? FIXME
    • apply_attribute myclk_attr -objects [get_ports DAT_1]
  • Constrain i/p Port DAT_1 with virtual clk =>We create virtual clk, when the port is being driven by a clk that is not an i/p clk to our block. First create virtual clk and define it async to all other clks. Next define a clock attr and associate it with this virtual clk. Finally apply this clk attr to the i/p Data port.
    • create_clock -name VIRTUAL_CLOCK_0 -period 2.0 => creates virtual clk
    • set_clock_group -asynchronous -group { VIRTUAL_CLOCK_0 } => define async to all other clks
    • define_attribute -name VIRTUAL_CLOCK_0_ATTR => define attr
    • set_clock_attribute VIRTUAL_CLOCK_0_ATTR -clocks { VIRTUAL_CLOCK_0 } => apply attr to virtual clk created above. So, it becomes clk attr now
    • apply_attribute VIRTUAL_CLOCK_0_ATTR -objects { DAT_1 } -add => Now, apply above clk attr to data port. Implies data port is being fired by this clk.
  • end_constraints_scope

 

Constraints: All i/p ports need to be constrained.

  • Input clk ports: I/P ports which are clk port, need to have clocks defined,
  • Input non-clk ports: All other non-clk input ports need to have one of the below constraints:
    • Driving clk specified for i/p ports. 2 ways to do this (assuming create_clk, etc are already done):
      • NEWER Style: apply_attribute AUTO_VIRTUAL_CLOCK_1 -objects { IN_PORT1 } -add
      • OLDER Style: set_input_delay -clock CLK_1 20 {PORT_1 PORT_2} => set i/p delay of 20ns on i/p ports specified, where they are being clocked by CLK_1, i.e i/p signal arrives 20ns after the rising edge of CLK_1
    • I/P port constrained using set_case 
      • set_case_analysis
    • I/P port constrained using static or quasi static value. This is less constraining than set_case, as this says that the value changes once in a while (under user control), and can be either 0 or 1.
  • Output ports: Output ports don't need to be constrained as they will be connected to i/p port of some other partition. So, they will be constrained as input ports in the other connected partition. However, when running at partition level, we still constrain it.
    • NEWER Style: Here, all of the process is the same as for constraining i/p ports. We define a virtual clk, make it async to all other clks, define and apply a clk attribute on it. Now,before we apply this clk attr to o/p port, we apply a sync attr => "-sync active" on this attr wrt the virtual clk defined. This makes  we define apply_attribute asyncOutput -objects  [get_ports -quiet OUT_PORT1 -filter {direction == out}] -add
    • OLDER Style: set_output_delay -clock CLK_2 5 PORT1 => set o/p delay of 5ns on o/p ports specified, where they are being clocked by CLK_2 on receiving side, i.e o/p signal should arrive 5ns before the rising edge of CLK_2.

and clocks need

 

Details
Published: Wednesday, 22 November 2023 01:32
Hits: 581

Sticky Deals:

Sticky deals are the ones where these deals are offered many times thru out the year, so I keep them in a separate section, and change any pertinent info. The regular deals which are offered once in a while are in separate "Deals" section. Go thru the Deals section too for the current year to see other deals.

 

 

Bank and Brokerage Bonus deals - All bank and brokerage bonus deals from 2025 (shown below) instead of a separate link in the Deals section (to save me time :)

National Banks (Available Nationwide): Look in bank account "National bank deal" bonus section for details of the offer: best National bank bonus

Regional Banks (Available Only in specific states): Look in bank account "Regional bank deal" bonus section for details of the offer: best Regional bank bonus

Brokerage Offers: Look in brokerage account bonus section for details of the offer: best brokerage bonus

 

 

Brokerage deals - All Brokerage bonus deals from 2025 have been moved to a common link (shown below) instead of a separate link for each bank bonus in the Deals section (to save me time :)

National Banks (Available Nationwide): Look in bank account "National bank deal" bonus section for details of the offer: best National bank bonus

 

 

Walgreens Free photo Deal => Multiple offers, about once a month for Free  8x10, 5x7 or 4x6 Photo

Look in "photo" under shopping section for details of the offer: photo

 

 

Lowes/HomeDepot Free Workshop for Kids once a month => on 1st and 3rd Saturday of each month from 9am to 12pm

Look in "kids stuff/activities" under shopping section for details of the offer: kids stuff/activities

 

 

HEB Gift Card Offers (in Texas stores only) - Buy Various GC on discount => about once a month

Look in gift card section for details of the offer: gift cards

 

 

Costco/SamsClub Gift Card Offers - Buy Various GC on discount => about once a month

Look in gift card section for details of the offer: gift cards

 

 

Walgreens Gift Card Offers - Buy 2 GC, get a $10 Walgreens GC free => Once every few weeks (mostly during end of year holidays): BEST GC DEAL YOU CAN FIND ANYWHERE !!

Look in gift card section for details of the offer: gift cards

 

 

OfficeDepot and Staples Visa/MasterCard Gift Card Offers - Online and in stores about once a month

Look in gift card section for details of the offer: gift cards

 

 

Topcashback: Multiple cash back offers throughout the year

Look in "cash back sites" section for details of the offer: cash back sites

 

 

Subway Offer - BOGO (select restaurants) offer multiple times a year => expires every few months

Look in "fast food" under food section for details of the offer: fast food

 

 

OfficeDepot / OfficeMax - Free Non Rechargeable AA/AAA batteries after rewards => offered every few months

Look in "electronics" under shopping section for details of the offer: electronics

 

 

Cell Phone Plan deals by MVNO => offered almost every month, with prices < $180/year for 1st year

Look in "phone services" under services section for details of the offer: phone service

 

 

Details
Published: Wednesday, 15 November 2023 04:10
Hits: 513

Black Friday 2023

This is an exclusive list of all BF 2022 deals. Even though I say "Black Friday deals", it refers to all the deals that go live during the holiday season, which is mostly from start of November to December end. Every year deals start earlier than last year, meaning this year deals have started surfacing in October itself.

Black Friday 2022 (last year) link is under shopping section here: Black Friday 2022

Anyway I'll list BF deals below. You still have extended return window for the holidays (most retailers like Walmart, Target, BestBuy allow you to return items until Jan 2021), so it's relatively low risk. You can always return the item if you find it at a lower price later in Dec or Jan.

Link for extended returns: https://www.doctorofcredit.com/extended-holiday-returns-from-amazon-walmart-best-buy-apple-target/

Best place to find all BF ads is from below links (too much advertisement makes it hard to navigate yell)

 

Deals:

 

Some good deals summarized (more details in bottom part of page along with deals)

  • Toys: Should see standard toys deals this year too.

 

 

 

 

 

Costco:

 

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