cortex M0

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Last Updated: Saturday, 28 March 2020 18:29

Published: Saturday, 28 March 2020 18:22

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Cortex M0 (ARMv6-M):
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Cortex M0 is the simplest, smallest and most popular core used in devices worldwide. NOTE: all registers are 32 bit wide here, even though most inst are only 16 bit wide.

For Cortex M0 inst set, Look in ARMv6-M arch reference manual. (For Cortex M3, look in ARMv7-M arch reference manual, chapter A4 and A5 (page 85 - page 417) for details and encoding)

ARMv6-M supports subset of T32 ISA = here all inst are 16 bit inst except these 32 bit inst: BL, DMB, DSB, ISB, MRS and MSR instructions. Not all inst in T32 ISA are supported by v6-M (it doesn't support CBZ, CBNZ and IT inst from T32 ISA, which are supprted by v7-M). As can be seen, T32 ISA (or even subset of T32 ISA as shown below) has lot more inst than Thumbs1 ISA.

these group of inst supported by M0: (Total inst =  86 inst listed in ARM cortex-M0 reference manual)
1. Arithmetic: ADD, ADDS, ADCS (Add with carry), SUB, SUBS, SBCS (subtract with carry), MULS, RSBS (same as NEG in Thumbs1)
2. Branch: B, BAL(unconditional), BL, BX, Bxx (conditional, various flavors = BEQ, BNE, BCS/BHS, BCC/BLO, BMI, BPL, BVS/BVC, BHI, BLS, BGE/BGT/BLE/BLT), BLX (link and exchange)
3. Data Xfer (load/store): MOV/MOVS/MVNS, MSR/MRS (MRS=rd special reg, MSR=wrt special reg), Unsigned load/store (LDR/STR, LDRH/STRH, LDRB/STRB), signed load (LDRSH,LDRSB),Load/store multiple (LDM/STM, LDMIA/STMIA, LDMFD, STMEA, PUSH/POP)
4. Logical: ANDS, ORRS, EORS, BICS (bit clear), ASRS (arithmetic shift), logical shift (LSLS/LSRS), RORS (rotate right), TST, reverse bytes (REV/REV16/REVSH) => 
5. Bit oriented (compare): CMP/CMN
6. Pack/unpack: SXTB, SXTH, UXTB, UXTH => there inst not there in 8051.

7. barrier: DMB/DSB/ISB (memory barrier), 

8. hint: SEV (send event), WFE (wake from event), WFI (wait for interrupt. this inst puts processor in sleep until wakeup event happens), NOP (Hint inst)
9. Misc: ADR, CPSIE/CPSID (enable/disable interrupt), BKPT (breakpoint), , SVC (supervisor call). . NOTE: none of these inst not present in Thumbs1 ISA.

Inst:
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B (branch):
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causes branch to target addr (PC) = current_addr + offset. offset can be even number (lsb=0), since all access are 16 bit aligned (is 16 bit in T1/T2 but 32 bit in T3/T4).
 T1 encoding: 16 bit [15:0]: [15:12]=1101, [11:8]=cond, [7:0]=8 bit imm value (-256 to +254 => values allowed are -128 to +127, but since msb=0, so it becomes -256 to +254 ).
 T2 encoding: 16 bit [15:0]: [15:11]=11100, [10:0]=11 bit imm value (-2048 to +2046).
 T3 encoding: 32 bit [31:0]: imm value = {S, NOT(J1 EOR S), NOT(J2 EOR S),imm6,imm11} = -2^20 to (+2^20-2)
   HW1 (lower 16 bits: [15:0]): [15:11]=11110, [10]=S, [9:6]=cond, [5:0]=imm6
   HW2 (upper 16 bits: [31:16]: [15:14]=10, [13]=J1, [12]=0. [11]=J2, [10:0]=imm11
 T4 encoding: 32 bit [31:0]: imm value = {S, NOT(J1 EOR S), NOT(J2 EOR S),imm10,imm11} = 2^24 to (+2^24-2)
   HW1 (lower 16 bits: [15:0]): [15:11]=11110, [10]=S, [9:0]=imm10
   HW2 (upper 16 bits: [31:16]: [15:14]=10, [13]=J1, [12]=0. [11]=J2, [10:0]=imm11

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3 addressing modes: [Rn, offset]: Rn=base reg
1. offset addressing: offset value added/sub from addr in base reg and used as the addr for mem access. base reg is unaltered.
2. Pre-index addressing: offset value added/sub from addr in base reg and used as the addr for mem access. but here base reg is written with the new addr.
3. Post-index addressing: addr in base reg is used as the addr for mem access. but here base reg is written with the new value which is offset value added/sub from addr in base reg.  



Alignment:
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For ARMv6-M, instruction fetches are always halfword-aligned and data accesses are always naturally aligned. So, inst fetch can only be done from addr whose botom bit=0. However, in compiled code we'll still see some addresses with the bottom bit set.  The bottom bit is used to show the destination address is a Thumb instruction.  It is not treated as part of the address. Each inst fetch brings in 4 bytes of inst. Since each inst is min 2 bytes, so each fetch can bring in 2 16bit inst, or 1 32 bit inst or 1 16 bit and part of 1 32 bit inst or parts of 2 32 bit inst. Inst prefetches are done in advance whenever there is a empty slot on AHB bus. inst to execute next is calculated as = (address_of_current_instruction) + (size_of_executed_instruction) after each inst. If that inst is already prefetched, it's executed else inst fetch is done for that address. Inst fetches are done with "WRITE" line set low. Data access are done with "WRITE" set high for writing to mem (inst STRB, STRH, STR), and set low for reading from mem (inst LDRB, LDRH, LDR). Naturally aligned means that an access will be aligned to its size.  So for a 4-byte access, it will be on a 4-byte boundary. So, if ld/st is STRB/LDRB,STRH/LDRH,STR/LDR, compiler will generate ld/st with addr aligned on byte or halfword or word boundary. So, if we do STRH from addr 0xF1 in C ode (because struct pointer points to that addr), then compiler will generate code for STRH from addr 0xF2 to make it HW aligned. (It didn't do str from addr 0xF0 as complier will only move to forward addr and not backward). Should software attempt an unaligned data access, a fault will be generated.

For C structs, the C standard says that struct has the same alignment as its most aligned member. So, if the struct has something defined as uint32_t, then it's starting addr will be aligned to Word. But individual members of struct will then be aligned as per the member's data size.

Cortex M0 pins:
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i/p pins
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reset pins: PORESETn(for jtag/sw), DBGRESETn, HRESETn, SYSRESETREQ(o/p)
clks: FCLK(for WIC), SCLK, HCLK, DCLK
irq: IRQ[31:0]
scan: SE (scan enable H during shifting and L during normal op) RSTBYPASS (bypasses internal reset sync so that ATPG tool can have controllability of reset flops)

o/p pins:
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HALTED: indicates that uP is in debug state.
LOCKUP: indicates that uP is in architected lockup state, as the result of an unrecoverable exception.
SLEEPING: indicates that uP is idle, waiting for interrupt on either IRQ[31:0], NMI or internal Systick (int entered due to WFI), or HIGH on RXEV (int entered due to WFE)
DEEPSLEEP: active when SLEEPDEEP bit in SCR set to 1. and SLEEPING is HIGH.
WAKEUP:

AHB bus:
i/p: HADDR[31:0], HBURST[2:0], HMASTLOCK, HPROT[3:0], HSIZE[2:0], HTRANS[1:0], HWDATA[31:0], HWRITE
o/p: HRDATA[31:0], HREADY, HRESP

M0 debug i/f can be configured for SW i/f or JTAG i/f but not both.
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debug: CDBGPWRUPACK(i/p), CDBGPWRUPREQ(o/p)
serial wire i/f: SWCLKTCK(sw clk), SWDITMS(sw data), SWDO(o/p), SWDOEN(swd o/p pad ctl signal),
JTAG i/f:
i/p: nTRST, TDI, SWCLKTCK(jtag TCK)), SWDITMS(jtag TMS)
o/p: TDO, nTDOEN(jtag TDO o/p ctrl signal)