RISC - V

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Last Updated: Monday, 12 February 2024 07:29

Published: Wednesday, 08 November 2023 17:31

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RISC - V (RISC - Five)

• RISC-V is the open source ISA available that you are free to use in your designs. No licenses, royalty, etc. Website for RISC-V is here: https://riscv.org/
• Many cores have been implemented using this ISA. You can download source code for Cores, SOC or even buy the processors which are built using this ISA. Link to download here: https://github.com/riscv/riscv-cores-list
• SiFive is one the front running company building processors based on RISC-V ISA. Lot of info on: https://sifive.com
• A video on basics of  RISC-V ISA: https://www.youtube.com/watch?v=m8DqCTogb8w

RISC-V ISA:

Official RISC-V ISA manual: https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf

Very good ISA intro => https://www.allaboutcircuits.com/technical-articles/introductions-to-risc-v-instruction-set-understanding-this-open-instruction-set-architecture/

RISC-V ISA is extensible so that it can be used for very basic microcontrollers, and also for complex super computers. In order to figure out what extension of ISA we are working with, we have a naming convention.

RV[###][ab..yz] => RV means RISC-V arch, [###] indicates width of reg file and size of user addr space, it may be 32, 64 or 128 bits. [ab...yz] indicates the set of extensions supported by an implementaion.

Extensions supported are as below: Number of reg and their width depends on the extension.

• I = Integer => This inst set is the only reqd extension in RISC-V, and defines 47 instructions.
• M = Integer Multiplication and Division
• G = General purpose which includes inst from I,M,A,F,D extensions
• C = an alternative compressed 16 bit encoding for a special subset of existing inst.
• A = Atomic extensions and many more std extension
• Many non-std extensions allowed too, and denoted as Xext.

ex:

• RV32I => Most basic RISC-V implementation. It's reg file is 32 bit, and supports Integer only.
• RV64GCXext => 64 bit (G=general purpose IMAFDC, C=16 bit compressed inst) + a non std extension
• RV32I/RV64I => they have 32 Int reg. F and D ext have 32 FP reg too. RV32E has only 16 integer reg for use in embedded devices.

RISC-V yields smallest code size for 32 and 64 bit processors compared to x86, ARM, MIPS, etc. RV32C or compressed version of ISA is the smallest code.

Reg File:

Reg: x0-x31. x0 is a "zero reg" hard wired to 0. NOTE: The ABI (application Binary i/f) names of the reg are different, and shown in link above.

Base Integer ISA (encoded in 32 bits) are for following:

• Addition:
• Subtraction:
• Bitwise op:
• Load/Store:
• Jump:
• Branch:

More inst:

• AMO (atomic mem op) perform read-modify write in a single atomic op.
• FENCE inst form a barrier. All inst preceeding FENCE must complete before proceeding. These are used t enforce program order.
• CSR (ctl and Status reg) inst and ECALL (environment call inst) to change privilege modes.
  • MM has ~17 CSR. (ex: Misa(m/c ISA reg), mstatus(m/c status), etc)

Modes:

Modes are privilege levels supported by RISC-V. We have 3 modes.

• Mode 3 or Machine mode (MM) is the highest privilege mode and the only required mode.
• Mode 2=Hypervisor,
• Mode 1=Supervisor,
• Mode 0=User/application.

These modes are also put as levels which correspond to diff combo of modes -  level 1 to level 4.

RISC-V also supports Virtual memory allowing for sophisticated mem mgmt and OS ctl (as Linux, etc). This requires an S-Mode implementation - Sv32, Sv39, Sv48 corresponding to 32 bit, 39 bit and 48 bit virtual mem. Physical mem protection is also supported for up to 16 regions, where we can restrict access to those regions.

RISC-V supports interrupts. CSR reg used to enable/disable specific interrupts or to see the status of any interrupt.