Audio/Video Bus
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- Last Updated: Saturday, 16 March 2024 12:47
- Published: Monday, 12 August 2019 20:38
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Audio/Video Bus Standards:
There are many bus and protcols designed specifivally for transferring audio and video data from one device to the other. Some of the common ones you might have heard are HDMI, MIPI, etc. Mostly, it's the video part that takes most of the bus bandwidth, and so these protocol are also called display protocols. We already looked at Audio only Bus Standards as I2S, TDM, PDM, etc. Before we get into these Audio/Video bus specs, let's get some display panel basics, as that gives us some understanding of how these bits transform to form images on LCD/LED panels that you have on your devices.
Display panel basics:
This link shares some basics:
Each memory location on the frame buffer corresponds to a pixel on the LCD panel. A 1024 x 600 resolution display (1280 columns x 600 rows) requires 614400 memory locations, with each location having a number of possible colors. The number of bits needed to describe the available colors is called bits per pixel (bpp). For example, 16 bpp can describe 65536 colors and 24 bits can describe 16777216 colors (known as true color). HDR standard defines 10 bit per color resulting in 30 bits per pixel, or about a billion colors. These are high end display panels. A panel with 614400 24-bit locations requires a 1800 KB frame buffer. The panel is continuously refreshed, typically at around 60 Hz, from the contents of the frame buffer memory. So, this frame buffer will need to be updated with new pixel data at the same rate.
The diagram on link above shows VSYNC signal that needs to be asserted every frame, and HSYNC that needs to be asserted every row. At each pixel clk, we send RGB data.
Resolution is usually described in terms of rows. So, 480p means 480 rows. However, with advent of 4K, we describe resolution in terms of columns. For HD screen (or 720p = 1280 columns x 720 rows), we'll need clcok running atleast 1280x720 times for each frame (assuming RGB bits are driven in parallel, and ignoring porch) => 921.6K => Now the frame needs to refresh @60Hz => 921.6K*60 clk pulses per second = 55.3MHz. If we have only single lane to drive all 24 bits for RGB, then this clk will need to be 24*55.3 = 1.3GHz. This is a very high requirement for 3Gbps for just HD display. Full HD (FHD or 1080p = 1920 columns x 1080 rows, FHD may be called 2K as it has 2K columns. It's 1/4th the resolution of 4K) and 4K (3840 columns x 2160 rows or 4096 columns x 2160 rows) have even higher requirement. In such cases, we use YUV format instead of RGB to reduce BW requirement. We may also use compression, as well as multiple data lanes. Still, clk needs to be in GHz range for 4K. That's why differential signaling used for driving these signals, since at these speeds, data fidelity can't be maintained w/o differential signaling.
Link that explains more about display interface: https://www.usmicroproducts.com/blog/understanding-display-interfaces
Resolution and Refresh rates supported by display interface:
We assume 24 bits per pixel for a typical display monitor. For a 4K resolution and 30Hz refresh rate with 24 bit color depth, we need to transmit 3840*2160*24*30=6 Gbit/sec. This means the display interface or cable will need to support transmitting data at this high speed. So, we use multiple lanes, usually 4 or more lanes to transfer data. Even that will require clk speed of 6/4=1.5Ghz which is very high speed. We'll look at both low and high speed display interface. For a 8K resolution (7680 × 4320) and 60Hz refresh rate with 24 bit color depth, we need to transmit 7680*4320*24*60=48 Gbit/sec. These require clocks running in excess of 10GHz not only on ASIC, but also on cable or long wires. This is very difficult feat to achieve, but has been done recently as of 2020 to support BW of 100 Gbit/sec.
Display communication protocol:
MIPI (mobile Industry Processor Interface): It's a non-profit org formed by alliance of various big companies. They have spec which define device interface technology. Initially, it was for mobile devices, but now encompasses PC, camera, automotive, etc. They define i/f spec b/w processor and camera, display, RF, battery, etc. Most common i/f:
- Display Serial Interface (DSI):
- Camera Serial Interface (CSI):
- System Power Management Interface (SPMI):
DSI:
DSI specifies high speed differential signaling for display controllers. Bus includes 1 CLK lane and 1 or more data lanes. Each lane is 2 wires (pos and neg due to differential signaling, both for clk and data). All lanes travel from the DSI host to the DSI device, except for the first data lane (lane 0), which is capable of a bus turnaround (BTA) operation that allows it to reverse transmission direction. When more than one lane is used, they are used in parallel to transmit data (i.e 4 lanes means 4 bit data transmitted in parallel).
So for basic 1 Lane DSI, we have 4 signals: clk (CLK_N, CLK_P) and data (DATA0_N, DATA0_P).
The link operates in either low power (LP) mode or high speed (HS) mode. In low power mode, the high speed clock is disabled and signal clocking information is embedded in the data. In this mode, the data rate is insufficient to drive a display, but is usable for sending configuration information and commands. High speed mode enables the high speed clock (at frequencies from tens of megahertz to over one gigahertz) that acts as the bit clock for the data lanes. Clock speeds vary by the requirements of the display.
The communication protocol describes two modes of transmission - video mode and command mode.
1. video mode: this is used to drive frames directly containing each pixel RGB values. This is used when external display doesn't have frame buffer to store frames, so frames are passed directly to display with appr panel timing (panel timing being generated by the processor or SOC). New frames are driven for each panel refresh (i.e 30 or 60 times per second), or else the image will be lost. Image data on the bus is interleaved with signals for horizontal and vertical blanking interval. Image data is only sent in HS mode. When in HS mode, commands are transmitted during the vertical blanking interval.
2. command mode: This is used to send cmds to update frame buffer in external display. Here pixel data is not driven directly, as frame buffer stores the pixel data and refreshes it. Here panel timing is generated by the display controller itself, instead of by the processor. New refresh data is send via set of cmds. So this mode is power friendly, as frames don't refresh that often, saving a lot of traffic on i/f. Even when they refresh often, not all pixel data changes, so only few pixels may be transmitted.
In cmd mode, there are 2 sets of instructions - DCA and MCS. The Display Command Set (DCS) is a set of common commands for controlling the display device, and their format is specified by the DSI standard. The Manufacturer Command Set (MCS) is a device-specific command space whose definition is up to the device manufacturer. The packet format of both sets is specified by the DSI standard. Packets are composed of a DataID, Word count, ECC, Payload and CRC. Commands that require reading data back from the device trigger a BTA event, which allows the device to reply with the requested data. A device cannot initiate a transfer; it can only reply to host requests.
CSI:
CSI specifies high speed differential signaling for camera modules. It interfaces processor and camera sensor. Same signals as in DSI.
High Speed Display communication protocol:
Besides the display interface we talked above, we also have high speed display interface that are used in TV, computers, gaming consoles to connect display src to display monitor. Here's a link to Video connectors: https://en.wikipedia.org/wiki/List_of_video_connectors
These transfer data at rate of 10's of Gbit/sec. Some of the common ones are:
- DVI (digital Visual Interface):
- VGA (Video Graphics array):
- HDMI (High Definition Multimedia Interface): Very popular and commonly seen on TV, PC, etc.
- DP (Display Port): More common on high end gaming PC and gaming consoles. Competes with HDMI.
We'll look at each of these in separate sections.