Flash Memory

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Last Updated: Wednesday, 30 October 2024 22:08
Published: Wednesday, 01 September 2021 18:59
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Flash Memory:

flash Memory is non volatile memory used to store data. In contrast to SRAM and DRAM memory which are volatile (lose data when powered off), flash memory retain data. Examples would be your USB Memory stick, SD memory card, SSD, etc. Note, Hard drive (HDD) stored data using different mechanism by using magentics (similar to CD/DVD technology). These are going out of phase and not worth pursuing anymore. Flash memory have virtually replaced these.

The only problem with Flash memory is that their wrt speeds are slow, as they have to use elevated voltage to program the bits of memory.

There are 2 kinds of flash: NAND type and NOR type. NAND is the one that is getting more popular.

NAND Flash Memory:

An intro paper on Nand memory:

https://www.longdom.org/open-access/nand-flash-memory-organization-and-operations-2165-7866-1000139.pdf

There is an organization called "open nand flash interface" (ONFI), which provides spec for Nand Flash i/f as to what pins they should have, speeds supported, cmds, reg, etc. All Nand flash manufacturers adhere to this spec, as they are all part of this org. Big companies which are members of this org include Intel, Micron, Hynix, etc. ONFi spec started from version 1.0 in 2007, and is currently at version 5.0

this is their spec link for different ONFI versions: http://www.onfi.org/specifications

ONFI 4.1 spec is what most manufacturers have their Flash chips based on, that is what we'll refer to: https://media-www.micron.com/-/media/client/onfi/specs/onfi_4_1_gold.pdf

Data interface types: ONFI 4 spec supports four different data interface types. These 4 i/f are supported on the same chip for backward compatibility. Early Flash memory chips supported SDR, and then grdually started supporting DDR with faster and faster speeds. SDR refers to single data rate where data is transferred on only 1 edge of clk, while DDR refers to dual data rate where data is transferred on both edges of clk each cycle. So DDR data throughput is doubled compared to SDR. The 4 Data interface types are:

  1. SDR,
  2. NV-DDR,
  3. NV-DDR2
  4. NV-DDR3. 

They have different speed, timing, voltages, etc. Details are in ONFI doc.

These are some of the aspects of different data interface:

Data i/f VCCQ                
SDR                  
NV-DDR                  
NV-DDR2                  
NV-DDR3                  

 

Nand reliability:

There are many noise sources in flash Mem that can flip the state of a bit. There are many techniques employed to improve the reliability of Nand flash. Some of these are:

1. ECC (Error correcting code): ECC is used heavily to correct these errors. There's a large area devoted to ECC.

2. Write leveling: Bitcells wear out after a certain number of writes. So, write leveling is done so that bits which are being less written are spread around so that they are written more.

3. Many other misc techniques.

 

 

Basics of Nand Flash:

Target: A device contains 1 or more targets, where each target is controlled by 1 CE_n (chip Enable) signal. 

LUN (Logical Unit): A target is organized into one or more Logical unit called LUN. A logical unit (LUN) is the minimum unit that can independently execute commands and report status.  Specifically, separate LUNs may operate on arbitrary command sequences in parallel. A LUN contains at least one page register and a Flash array. The Flash array contains a number of blocks. Each block contains a number of pages.

Page: Unlike most memory technologies, NAND flash is ordered in pages which are written and read as a unit. The elementary unit of operation for a NAND Flash device is one page of data with control commands of the whole block (multiple pages). Therefore data can be written only to one page at once. As shown in Figure 5, a page is defined as cells linked with the same word line. This is the smallest programmable unit physically made up of a row of cells.  A page is the smallest addressable unit for read and program operations. Erase takes place on a block basis. The page size is typically 2 or 4 Kbytes,

Block: As explained above, a group of pages is called a block. A block typically contains of 32 or 64 pages (has to be a power of 2). A block is the smallest erasable unit of storage. The reason for this is that all the NAND strings  share  the  same  group  of word lines that are erased together.  

Plane: The  NAND  Flash  memory  is  composed  of  the  blocks  of  pages,  which  could  be  grouped  into  a  flash  plane.  Depending  on  the  kind  of  device,  planes  are  in  principal  mutually  independent.  A  single  plane  covers  local  buffering  for read and program data, and can process operations in parallel.

Nand operations:

NAND flash devices carry out three basic operations of rd, wrt and erase.

  1. program a page: During  the  page  program  operation,  a  page  is  written  into  the  data  register  and  then  programmed  into  the  memory  array.  First  the  page  address  and  the  command  word  are  moved  into  the  device  followed  by  the  programming  data.  
  2. erase a block: Flash  memory  allows  only  two  states:  erased  and  non-erased.  A  given bit of data can only be written when the media is in an erase state. When data is written into, the bit is considered dirty and unusable for other write operations. A write operation in any type of flash device can only be accomplished on an erased unit and so a write operation must be preceded by an erase operation. In the erase state, a byte can be either all zeroes or all ones depending on the kind of flash device.
  3. read a page:Bits  in  a  flash  cell  are  read  by  changing  the  voltages  on  rows  and  columns  of  cells  followed  by  assessing  the  results.  In  a  page  read  operation, a page is moved from memory into the output data register.

These operations shown above are carried out in steps. In general, these are the steps:

  1. 1st step, cmd is sent out on Data lines,
  2. 2nd step. then row/col addr are sent out on data lines, Row addr is used to address pages, blocks, and LUNs. The column address is used to access bytes or words within a page, i.e. the column address is the byte/word offset into the page. Some op like "block Erase" require only col addr, so only 1 cycle addr issued. But some ops require both row and col addr, so 2 cycles needed with col addr issued in 1st cycle and row addr in 2nd cycle.
  3. 3rd step. Finally,  the value to be read or written is put on data lines. 

 

NOTE: In a NAND Flash device read and program operations take place on a page basis rather than on a byte or word basis like NOR Flash. This dictates the need to have the size of data I/O register equal to the page size.

NAND Flash memory is controlled using set of commands, these sets  of  commands  differ  from  memory  to  memory.  There  are  many  commands,  some  are  universal  to  all  NAND  Flash  manufacturers  while some commands are manufacture specific and supported only by a  few  devices.  According  to  the  Open  NAND  Flash  Interface  (ONFI)  Standard there is a list of the basic mandatory command set. The most common  commands  are   ́program ́,   ́read  data ́,   ́erase ́,   ́reset ́, etc.

 

 

Timing diagrams: Attach hand written notes