Before we get into complicated stuff, let's start from the simplest buliding bllock, atom. Section 3 of Feymann lectures deals with quantum physics that we deal with when talking about atoms. Feynman has one of the best material on Physics.

http://www.feynmanlectures.caltech.edu/

 

ATOMS:

Atom is the smallest entity that exists for any material. It has neutrons and protons in the nuclues, and an electron circulating around it in orbit. These would seem like particle, but modern quantum theory states that quantum scale objects have wave-particle duality, and exhibit both wave like and particle like properties. There have been many controversies over this wave-particle nature of objects, but is now generally accepted. Bigger the size of object, it's wave characteristics become so small, that it acts like a particle fr most practical purpose. However, for very small objects, as electrons, wave characteristics are noticeable. Similarly all electromagentic radiation (i.e light, heat), etc are assumed to hold both wave and particle characteristics to help explain many phenomenon which can't be explained by assuming only a particle mode, or only a wave model.

For our purpose, we will treat all electron, proton and neutron as particles, with the understanding that they show wave properties. Electrons have -ve charge, protons have +ve charge, and neutrons are chargeless. All of them have mass, but their mass is too small (neutron/proton have 1800 times greater mass than electron, but still small). So, gravitational forces between these masses is too small. They are held together via electrostatic forces (forces b/w opposite charges).

electron: mass = 9.1 x 10^-31 kg = 0.0005amu, charge = -1.6 x 10^-19 C, (electron lot smaller than neutron/proton, so mostly viewed as wave)

proton: mass  = 1.7 x 10^-27 kg = 1.007amu, charge = +1.6 x 10^-19 C, 

neutron: mass = 1.7 x 10^-27 kg = 1.008amu, charge = 0 C,  (neuton slightly heavier than proton)

In any atom, neutron and proton are in center nucleus, while electron is in circular orbit. Number of protons and electron are equal, resulting in 0 charge for an atom. This is also called "atomic number" of atom (num of electrons).

With any atom, energy is needed to break it apart into electrons and protons, That means some energy was supplied to form an atom (electron and proton joined to form an atom). They were formed right after the "Big Bang" when our known universe originated from pure energy some billions of years ago. The energy was converted to the elementary or sub atomic particles (quarks, gluons, leptons etc...). These condensed to form electrons and protons. Very soon, a proton and an electron met, and formed a hydrogen atom (no neutron, so mass=1amu). The neutron came about in a similar manner, and condensed with neighboring electrons and protons to form a complex mixture of the isotopes of hydrogen and helium (helium has 2 neutrons, 2 protons and 2 electrons, so mass=4amu). From this sprang everything else. That is why we find hydrogen and helium in abundance everywhere in universe, since these were the earliest and rudimentary atoms formed.

We can calculate total energy present in any isolated atom, by calculating the electrostatic energy b/w proton and electron, and kinetic energy of electron. We postulate that this total energy has to be -ve, since we have to supply energy to it, to break it. If total energy was greater than 0, then electron would be free to roam around, w/o being bound to the proton.

Electrostatic potential energy: Two charges at infinite distance are assumed to have 0 potential energy. they have attractive/repulsive forces depending on polarity of charges. Let's assume there are 2 charges +q and -q at infinite distance. They have 0 potential and 0 kinetic energy. They start attracting each other because of attractive force. Since Work=F*distance*cos(theta), they do work W=∫ F*dx = ∫ k*q1*q2/r^2 * dx. Integrating this we get W= - k*q1*q2/distance, which represents the final electrostatic potential energy stored in the system of these 2 charges, as +ve work was done on the +q charge. This work done didn't get lost anywhere, and by conservation of energy has to be stored somewhere. The +q charge will finally have some velocity and acceleration (due to force F acting on it), but the final velocity doesn't account for all of the energy. Since the system had 0 initial energy (at infinite distance and zero velocity), final energy also has to be 0. Since final kinetic energy is +ve, an equivalent -ve energy has to be there, which is what is stored as electrostatic potential energy.

When electron and proton come together from infinity to form an atom, we see that the final kinetic and potential energy is not 0. Again, this is expected, since they formed a bond by giving out energy, and so total energy goes -ve. This means to get this atom to have 0 net energy, we need to apply a +ve energy of that value, and then this atom will break apart into an electron and proton. Let's do this calculation for hydrogen atom.

Bohr's model: Very early, Bohr gave a simplified model of what radii, electron are circulating around nucleus. Ground state is the lowest state available for electron which is at radii R = 5.3 * 10^-11m = 0.53A. This radius can actually be calculated by getting total energy of atom (PE+KE), and then minimize this energy. PE decreases as electron gets closer to proton, but KE increases because of velocity increase (required due to uncertainty priniciple, which states that as electron gets coser, uncertainty in it's position is reduced, which requires corresponding increase in velocity to keep the product above the limit). It will turn out that min energy happens at radius R=0.53A.  Look at Feymann's lectures III-02 on the derivation.

centripetal force for electron to revolve around proton is provided via electrostatic force. F = m*v^2/R = k*q^2/R^2 => m*v^2 = k*e^2/R (e is the charge of an electron)

KE = 1/2*m*v^2 = 1/2*k*e^2/R

PE = -k*q1*q2/R = -k*e^2/R

Total energy = KE+ PE = -1/2*k*e^2/R = -2.2*10^-18J = -13.6eV (NOTE: KE is 1/2 of PE but of opposite sign. If KE was same as PE then net energy would have been 0)

1eV=1.6*10^-19J since Force F = q*E = q*V/d (For electric field E= V/d, where V=potential difference b/w 2 points and d=distance b/w them). Then Work W=F.d=q*V/d*d = q*V = 1.6*10^-19*1V = 1.6*10^-19J = 1eV

So, it will take 13.6eV of energy to ionize an hydrogen atom (i.e remove an electron from ground state).

-13.6eV is the lowest possible energy state. An electron can't get any closer than this to the nucleus. An electron can get into larger radius, but then it's speed will decrease (in accordance with hisenberg uncertainty principle). The total energy in this case will increase (though will still be -ve). It turns out that electron can only be in certain discrete radius (i.e it's not possible for it to be in any arbitrary radius). These distinct radius gives rise to distinct energies. We call these different enery levels. This is what is referred to as quantum physics, as electron energy levels are quantized. Of course the highest energy can be anything infinite, but at that point electron and proton are separate and electron is moving at infinite speeds. For our purpose, highest energy level is 0, which is the state where electron and proton just separated, and electron is at rest (no KE). We call this energy level Einfinite. The lowest energy level (-13.6eV) is called E0 (ground state), next one is called E1 and so on (highere states called as excited states, which they get to by absorbing energy from outside. 2 primary ways to excite an electron are thru absorbing light and thru collisions) . In energy state E100 or higher, electron is so loosely bound to the atom, that any small perturbation or external energy will pull the electron out.

En=-E0/n^2 where n is the energy state = 1,2,3 ...

So, E1=-E0/4 = -3.4eV (i.e if electron was in this state, ionization energ = 3.4eV only)

Periodic table shows atoms with 1 electron, all the way to atoms with 100 or more electrons. Each of these atoms consitututes a different element, and that is all the elements we know about. Interesting that just having a different number of electron changes the material so drastically (i.e aluminum vs silicon). Electrons can be in state 1s, 2s, 2p, 3s, 3p, 4s, etc. s states can have max of 2 electrons, while p states can have max of 6 electrons. 1s states correspond to n=0, 2s/2p states to n=1, 3s/3p to n=2 and so on. For a simple atom like hydrogen which has only 1 electron, all states in same "n" have same energy. i.e all states in 3 (3s,3p,3d) have same energy E2=-13.6/9=-1.5eV, However for atoms that have multiple lectrons, these electrons interact with each other, giving rise to splitting of energy levels within same n. So, 2p states are little higher on energy diagram than 2s states, but still lower than 3s states. Detailed diagrams in II-19 of Feymann's lectures. This is why s states are occupied before p states, as electrons always occupy lowest energy states. One important observation is that from states 3s and beyond, energy states start getting closer to each other (E=E0/n^2), which causes many of these energy states to overlap each other. This results in 3d being at higher energy than 4s states. This is why 4s states are occupied before 3d states, as electrons always occupy lowest energy states. More complicated maths involving schrodinger eqn is needed here.

For helium, which has 2 electrons, E0=-24.6eV (so 24.6eV needed to ionize it, or remove 1 electron). If we want to ionize it further, by removing the last electron, ionization energy=-54.4eV. So any further ionization always requires more energy.

For silicon, which has 14 electrons, ionization energy = 8.1eV. Ionization energy is b/w 5-10eV for most elements except 10 elements in 1st and 2nd row of periodic table (since electrons are further out, so lower energy needed).

Collection of atoms:

Above theory applies to isolated atoms. However, when 2 atoms come close together, there is an interaction between the orbits of their electrons. This interaction causes a splitting of each individual energy level into two slightly different levels. The atoms in almost every crystalline solid are so close together that the energy levels produced after splitting due to interaction between the various orbits of different electrons will be very large and so close together as to form a band.

Consider imaginary formation of a diamond crystal from isolated carbon atoms. Link: http://www.engineeringenotes.com/electrical-engineering/conductivity/energy-bands-in-solids-conductivity-electrical-engineering/33944

Each isolated carbon atom has an electronic structure 1s2 2s2 2p2 in the ground state. Each atom has available two 1s states, two 2s states, six 2p states and higher states. If we consider, N atoms, there will be 2N, 2N and 6N states of type 1s, 2s and 2p respectively. As the interatomic spacing decreases, their energy level split into bands, beginning with the outer shell, i.e., n = 2. As the 2s and 2p bands grow, they merge into a single band composed of a mixture of energy levels. This band of 2s-2p levels contains 8N available states.

As the distance between atoms approaches the equilibrium interatomic spacing of the diamond, this band splits into two bands separated by an energy gap Eg. The upper band (conduction band) contains 4N states, as does the lower band (valence band). Thus, apart from the low lying and tightly bound 1s levels, the diamond crystal has two bands of available energy levels separated by an energy gap Eg wide which contains no allowed energy levels for electrons to occupy. These energy bands are actually made up of many discrete energy levels which are too close together to resolve. Within a band the number of levels is of the order of the number of atoms in the crystal, so although electrons are actually restricted to these energies, they appear to be able to take on a continuum of values. 

The lower 1s band is filled with the 2N electrons which originally resided in the collective 1s states of the isolated atoms. However, there were 4N electrons in the original isolated (n = 2) shell (2N in 2s and 2N in 2p states). These 4N electrons must occupy states in the valence band or the conduction band in the crystal. At 0 K the electrons will occupy the lowest energy states available to them. In the case of diamond crystal, there are exactly 4N states in the valence band available to the 4N electrons. Thus at 0 K, every state in the valence band will be filled, while the conduction band will be completely empty of electrons.

In an insulator and pure semiconductor, lower band is completely filled and the upper band is completely empty. The energy of the forbidden gap is denoted by Eg. The conduction takes place only when the electron in valence band jumps to the conduction band. In other words, the electron in valence band requires energy equal to Eg to jump to the conduction band. When the electron jumps from the valence band to the conduction band, then a vacancy electron called a hole is created in the valence band. Since hole is a deficiency of an electron and hence is positively charged. The forbidden energy gap in an insulator is of the order of 5 to 10 eV. The amount of energy cannot be imparted to the electrons in the valence band and hence the electron cannot jump from the valence to conduction band. Therefore, conduction is not possible in the insulators. The forbidden energy gap in case of semiconductor is usually, of the order of 0.75 to 1 eV. This amount of energy can be easily imparted to the electrons in the valence band by thermal agitation of the crystal lattice. Thus, with the increase in temperature, many electrons from the valence band acquire the required amount of energy to jump to the conduction band and these results in the increase of electron hole pairs. The forbidden energy gap Eg is the energy required to break the covalent bands so as to make the electron free for conduction. In a conductor, this bandgap is of order of 0.01eV, so virtually all electrons in valence band avilable for conduction.

 Very good explanation on spliting of energy bands => https://www.youtube.com/watch?v=-lHXZk5M6cI

 


 

Vesta comes with the qflow package. Here we try to do a stand alone vesta installation, as it's very simple to do:

In dir where you have qflow downloaded, do this:

cd qflow-1.3.13/src

vesta.c, hash.c and hash.h are the 3 files used to generate binary vesta.

Copy these files + Makefile in some temporary dir, and generate vesta binary over there, so as to not mess the original qflow dir.

mkdir vesta_temp; cd vesta_temp; cp vesta.c, hash.c, hash.h, Makefile

Run Makefile in this dir to generate executable =>

make vesta

It runs this rule:

vesta$(EXEEXT): vesta.o $(HASHLIB)
$(CC) $(LDFLAGS) vesta.o $(HASHLIB) -o $@ $(LIBS)

These are the cmds seen on screen =>

cc -g -O2 -DPACKAGE_NAME=\"\" -DPACKAGE_TARNAME=\"\" -DPACKAGE_VERSION=\"\" -DPACKAGE_STRING=\"\" -DPACKAGE_BUGREPORT=\"\" -DPACKAGE_URL=\"\" -DSTDC_HEADERS=1 -DHAVE_SETENV=1 -DHAVE_PUTENV=1 -DTCLSH_PATH=\"/usr/local/bin/tclsh\" -DQFLOW_MAGIC_PATH=\"/usr/local/bin/magic\" -DQFLOW_NETGEN_PATH=\"/usr/local/bin/netgen\" -DQFLOW_QROUTER_PATH=\"/usr/local/bin/qrouter\" -DQFLOW_GRAYWOLF_PATH=\"/usr/local/bin/graywolf\" -DQFLOW_YOSYS_PATH=\"/usr/local/bin/yosys\" -DQFLOW_OPENTIMER_PATH=\"\" -DQFLOW_OPENSTA_PATH=\"\" -DQFLOW_VERSION=\"1.3\" -DQFLOW_REVISION=\"13\" -c vesta.c -o vesta.o

cc -g -O2  -DPACKAGE_NAME=\"\" -DPACKAGE_TARNAME=\"\" -DPACKAGE_VERSION=\"\" -DPACKAGE_STRING=\"\" -DPACKAGE_BUGREPORT=\"\" -DPACKAGE_URL=\"\" -DSTDC_HEADERS=1 -DHAVE_SETENV=1 -DHAVE_PUTENV=1 -DTCLSH_PATH=\"/usr/local/bin/tclsh\" -DQFLOW_MAGIC_PATH=\"/usr/local/bin/magic\" -DQFLOW_NETGEN_PATH=\"/usr/local/bin/netgen\" -DQFLOW_QROUTER_PATH=\"/usr/local/bin/qrouter\" -DQFLOW_GRAYWOLF_PATH=\"/usr/local/bin/graywolf\" -DQFLOW_YOSYS_PATH=\"/usr/local/bin/yosys\" -DQFLOW_OPENTIMER_PATH=\"\" -DQFLOW_OPENSTA_PATH=\"\" -DQFLOW_VERSION=\"1.3\" -DQFLOW_REVISION=\"13\" -c hash.c -o hash.o

cc vesta.o hash.o -o vesta

Or run this single cmd: cc -g -O2 hash.c vesta.c -o vesta => this will generate vesta executable

NOTE: for some reason, compilation shows error with this line when run as single cmd above (one of the defines -D is required):

vesta.c: In function ‘main’:
vesta.c:3795:31: error: expected ‘)’ before ‘QFLOW_VERSION’
  fprintf(stdout, "for qflow " QFLOW_VERSION "." QFLOW_REVISION "\n");
                               ^

Just comment out this line and compilation goes fine => //fprintf(stdout, "for qflow " QFLOW_VERSION "." QFLOW_REVISION "\n");

Now run vesta providing liberty file and netlist

./vesta map9v3.rtlnopwr.v /usr/local/share/qflow/tech/osu035/osu035_stdcells.lib => verilog netlist is the one generated by qflow after synthesis/PnR stage.

vesta.c:

main routine:

1. process cmd line arguments

2. Read liberty file => libertyRead(flib, &tables, &cells);

    liberty file table values get stored in linked list "tables" (struct lutable) and "cells" (struct cells)

3. Read verilog netlist => verilogRead(fsrc, cells, &netlist, &instlist, &inputlist, &outputlist, Nethash);

  • Parse thru verilog netlist. Look for module/endmodule keywords for start or end of module.
  • Then look for i/p, o/p pins and assign those i/o nets to inputlist (struct connect) and output list (struct connect).
  • Then parser parses lines like this "CLKBUF CLKBUF_1 ( .A(clock), .Y(clock_buf4) );" Here CLKBUF is instance definition, and CLKBUF_1 is instance name. Both are parsed and instlist (struct instance) is created for CLKBUF_1, whose reference inst is CLKBUF. Then pin names A,Y are parsed and "struct connect" is created for each pin, here for "clock" with direction as i/p pin, and for "clock_buf4" with direction as o/p pin. netlist (struct net) is created for the nets connecting to these pins.

4. create internal links => createLinks(netlist, instlist, inputlist, outputlist);

5. Report on max delay paths

6. Report on min delay paths

5. Report on max delay paths

6. Report on min delay paths

 

 

DFT: Design for Testatbility

Any chip that is fabricated is going to have some defects during fabrication, which will cause some of the transistors or wires on the chip to not function properly. This may cause the chip to fail. One way to check if the chip manufactured is good or not, is to run thru the same functional patterns on the chip pins that the chip is going to go thru when it's in operation.

For small chips this method may work, but for large chips, it's practically not feasible for 2 reasons. First, there may be billions of such possible patterns on chip pins that we may have to aplly, which is time prohibitive. Secondly, it may still not find out all bad devices or bad connections in chip, since those patterns may not target 100% of the chip devices.

Without having 100% check to test each and every transistor and each and every connection, we can never be sure if the chip being shipped is 100% functional or not. This is where DFT comes. DFT simply means adding extra logic on chip so as to allow us to test the whole chip. DFT is a broad field by itself, an you will usually see thousands of job postings just for DFT engineers.

In this section, we will go thru the basics of DFT,

IEEE 1500:

IEEE 1500 defines a standard for test access of cores within a big chip. For small designs, we just do connections at top level, and pass on signals from 1 module to other. But for big designs, it can get very complex. For such designs, we treat each block as a chip in itself, having it's own controller for dft purpose, which handles all internal details of dft. Then, at top level we justhave a top level 1500 controller, which connects and controls these block level 1500 controllers. All connections are controlled via JTAG pins. These pins go into top level TAP controller, which processes and passes all the appr signals to each block.

We define standard port interface for IEEE 1500, to connect different blocks. Most signals are prefixed with W which stands for wrapper. WIR = wrapper instruction reg, while DR = data reg (WDR or wrapper data reg name not used for whatever reason). These IO signals are:

WRCK/WRCLK = Clock. This is actually connected to chip JTAG pin TCK.

WRSTN = Reset (active low). This resets all reg in WIR to 0, indicating func mod. This is actually connected to chip JTAG pin TRSTN.

SHIFTWR/SHIFTDR = Shift WIR or DR. With this signal high, Shift reg gets connected b/w WSI and WSO and starts getting values shifted in/out

UPDATEWR/UPDATEDR = Update WIR or DR. With this signal high, Update reg gets updated with values in shift reg.  These signals coming out of Update reg thenget stored in bunch of internal reg, which control all test related stuff in Func logic (i.e bist control signals, bypass, etc)

SELECTWIR = Operate on WIR. (we can have multiple SELECTWIR1, SELECTWIR2, etc if we have multiple partions within WIR, which we want to activate separately)

WSI / WSO Scan In/Out Data. These are single bit line for scanning data in and out of IR/DR. These are connected to chip JTAG pin TDI/TDO via daisy chain. First block's WSI comes from top TAP controller, which in ultimately connected to TDI pin, WSO pin connects to next block WSI pin, and so on. Last block's WSO pin goes to top TAP controller, which finally connects to chip TDO pin. The i/p pin WSI is captured on +ve clk edge, while o/p pin WSO is fired on -ve clk edge. This follows the same convention as for all other pins of JTAG which are fired on -ve edge, but captured on +ve edge of clk.

WPI /WPO Parallel In/Out Data. These are multi bit bus, and used for scanning data in and out of functional flops (i.e scan chain stitching of functional flops). These are same as SDI (scan Data in) and SDO (scan data out) pins that are used in designs for scan data in/out. The reason, we have a bus is to have mutiple chains of scan in/out for big designs (since they may have millions of flops, and shifting data in/out via just one pin is going to take hours). WPI/WPO are captured/fired on same clk edge as WSI/WSO.

 

See diagram.

Top level TAP:

We specify special JTAG inst to control the above signals at block level. We can define as many JTAG inst as needed to have control over various 1500 controllers in the design. We can have JTAG instructions for selecting specific 1500 controllers at block level ,

J1500I = JTAG 1500 inst for Inst Reg. This gets SELECTWIR signal high, and SHIFTWR or UPDATEWR signal high

J1500D = JTAG 1500 inst for Data Reg. This gets SELECTWIR signal low, and SHIFTDR or UPDATEDR signal high

Once you have all the pieces ready, we will download, qflow:

Head over to this link: http://opencircuitdesign.com/qflow/index.html

Download latest stable version that is under stable download link. I downloaded "qflow-1.3.13.tgz" (which was the latest version with release date of Mar 19, 2019). Extract it in a dir named "qflow-1.3.13". In this dir, we see a README file, which has all instructions for installing it:

cd qflow-1.3.13 => Now run below 3 cmds in this dir

1. ./configure => This will look for all tools that qflow needs. It shows configuration results at end.

Using yosys verilog synthesis tool at: /usr/local/bin/yosys
Using graywolf placement tool at: /usr/local/bin/graywolf
Using qrouter detail route tool at: /usr/local/bin/qrouter
Using Magic layout tool at: /usr/local/bin/magic
Using Netgen LVS tool at: /usr/local/bin/netgen
Using Vesta STA tool (internal)
Using Vesta STA tool (internal)

If some thing not found in std path, it will show warning: WARNING: Netgen LVS tool not found.  Use --with-netgen=<DIR>. We will need to fix this by downloading/installing that tool and specifying an alternate path for that tool (if it exists in some other dir).


2. make => make is run. Last 2 lines indicating successful compilation are:

make[2]: Leaving directory `/home/proj/qflow-1.3.13/tech/gscl45nm'
make[1]: Leaving directory `/home/proj/qflow-1.3.13/tech'

3. sudo make install => This puts qflow executable in correct dir. It shows same last 2 lines as in "make" step above.

/usr/local/bin/qflow => qflow script put here

/usr/local/share/qflow/* => all qflow related scripts, etc put here

Run "which qflow" to make sure it shows "/usr/local/bin/qflow" as the path. Type "qflow" on cmdline, and it should show you a help menu.

Project:

Now, we will setup a "experiment" dir where we will get a small project going.

mkdir test_ex1
cd test_ex1
emacs map9v3.v => this creates a new blank file called map93v3.v. This small file is on tutorials link on qflow page. Copy contents from there to this file.
qflow map9v3 => run qflow on this module named "map9v3". Note we do not provide the name of verilog file, but just the name of top level module. Then it will look for module named "map9v3", which it will find in file named map9v3.v. Screen shows this o/p:

--------------------------------
Qflow project setup
--------------------------------

No technology specified or found;  using default technology osu035

No actions specified on command line;
creating qflow script file /home/kailash/Project/test_ex1/qflow_exec.sh only.
Uncomment lines in this file and source the file to run the flow.

The flow created a csh file called qflow_exec.sh file, which is very simple wrapper for calling individual steps in the flow. All of these asteps re commented. We can uncomment lines 1 at a time, and run the script, or copy cmds from this cript, and run that cmd directly on the shell. All output files are generated in same dir. These are the steps, running them 1 by 1:

1. Synthesis => runs synthesis using Yosys and generates verilog gate netlist map9v3.rtlnopwr.v, map9v3.rtl.v, and bunch of other files.

/usr/local/share/qflow/scripts/synthesize.sh /home/Project/test_ex1 map9v3 /home/Project/test_ex1/map9v3.v || exit 1

2. Placement => runs placement using graywolf

/usr/local/share/qflow/scripts/placement.sh -d /home/Project/test_ex1 map9v3 || exit 1

3. Timing => runs timing using vesta. This is initial timing run on placed design (with no routing info)

/usr/local/share/qflow/scripts/vesta.sh  /home/Project/test_ex1 map9v3 || exit 1

4. Routing => runs detailed routing using qrouter

/usr/local/share/qflow/scripts/router.sh /home/Project/test_ex1 map9v3 || exit 1

5. Timing => runs timing using vesta. This is final timing run on routed design (with all wire delays included)

/usr/local/share/qflow/scripts/vesta.sh  -d /home/Project/test_ex1 map9v3 || exit 1

6. Migrate => runs magic to generate final layout

/usr/local/share/qflow/scripts/migrate.sh /home/Project/test_ex1 map9v3 || exit 1

7. DRC => runs drc using magic on final
/usr/local/share/qflow/scripts/drc.sh /home/Project/test_ex1 map9v3 || exit 1

8. LVS => run lvs using netgen
/usr/local/share/qflow/scripts/lvs.sh /home/Project/test_ex1 map9v3 || exit 1

9. GDS => run magic to generate gds
# /usr/local/share/qflow/scripts/gdsii.sh /home/Project/test_ex1 map9v3 || exit 1

10. cleanup => cleanup script to remove un-needed files
/usr/local/share/qflow/scripts/cleanup.sh /home/Project/test_ex1 map9v3 || exit 1

11. display => display final layout in gds using magic
 /usr/local/share/qflow/scripts/display.sh /home/Project/test_ex1 map9v3 || exit 1

 


Cadence IMC tool info:
---------------------------
IMC = Incisive Metrics Center. It is metrics anlysis tool for coverage (code, FSM and functional) analysis. It can analyze data generated from ICC (Incisive Comprehensive coverage) which is generated when irun is run with -coverage. Coverage file is generated in test_name/coverage/tests/*.ucd and *.ucm file

3 kinds of coverage:
1. Code coverage: consists of block, expresssion and toggle coverage
2. FSM coverage: coverage of all possible states and transitions in state machine.
3. Functional coverage: generated by inserting PSL, SystemVerilog assertions, or SystemVerilog covergroup statements into the code and simulating the design.

IMC reads metrics data from run dir which has all coverage database from single run. By default, metrics data is stored in:
cov_work/scope/*.ucm => model file. 8 digit hex is the checksum of design hier and code coverage metrics
cov_work/scope/test/*.ucd => data file. 8 digit hex is the checksum of design hier and func coverage metrics

By using option "irun -covworkdir coverage -covdesign tests -covtest <TEST1>", we set cov_work=coverage, scope=tests, test=TEST1. So, final coverage results stored in this dir:
coverage/tests/*.ucm
coverage/tests/TEST1/*.ucd

If we have multiple tests, we need to merge coverage results of all tests. To do this we run imc
imc -15.10-incisiv -batch -init imc_merge => -batch starts imc in cmd line interactive mode (otherwise it starts in gui mode)
imc_merge has these 2 lines:
merge test_*/coverage/tests/* -overwrite -out result
exit

This takes coverage results for all tests from "test_*/coverage/tests/*.ucm and <test_name>/*.ucd" and puts results in "cov_work/scope/result/*.ucm, *.ucd" (as specified in -out dir specified above).

Then run imc with the same version to look at coverage results:
imc -15.10-incisiv

imc window:
----------
on imc window, look in module interested in, and see "overall covered" results. This needs to be 100%. It's divided under 3 coverage: Code coverage (Block, Expression, Toggle), FSM coverage and Functional coverage.

Code coverage:
-------------
Block coverage:
Expresssion coverage:
Toggle coverage:

Expression coverage:
------
It shows terms T1, T2, etc. It looks for all possible 0/1 values of T1,T2,etc to see if everything is covered. tool should have entered that line in sim, by exercising whatever cond is needed to get there.
ex: state <= sel ? STATE1 : STATE0; It shows T1=sel, T2=STATE1, T3=STATE0. It looks for 8 possible combo of T1,T2,T3 from 000 to 111. If it says, it's looking for term T2=1, it means it's looking for STATE1 values of 0 and 1. STATE1 might be encoded as 001 => STATE1 is always 1. If STATE0 is encoded as 000 => STATE0 is always 0. Tool is smart to figure out that STATE1 can never be 0 and STATE0 can never be 1. So, it will automatically exclude these cond (shows as red with white line in b/w, reads "exclusion rule type = simulation time)

Exclusions:
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We can apply exclude to whole block by clicking "Exclude" button on top after selecting amodule (shows up as red dot on LHS of that block).
We can save exclusions in *.vRefine file by clicking on Analysis->Save Refine. Then we can load it back when opening new session of imc. That way we won't have to type exclusions again.

Exclusions rule types can be 2 types:
1. Analysis time:
2. simulation time:

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Vmanager:
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vmanager is verification tool suite. It used to be emanager, but now it's all combined as vmanager.

It lets automate the process of verification planning, regression, collecting results and displaying them in tabular format. Vmanager provides capability to launch IMC from vPlan window for detailed coverage reports

emanager:
--------
regresssion:
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To run regression, do this:
emanager & => once emanager is up, click setup, then start and then open one of *.vsif file that has regression script in it. On clciking ok, it starts regression. It will show the session window that shows tests run (and how many pass, fail, run, wait, timeout(or dropped from lsf queue)

top vsif file to run is veridian_regress.vsif. It has parameters and calls another vsif file which has list of tests.

veridian_regress.vsif:
----------------
session veridian_regression {
   top_dir: $ENV(MY_REGRESSION_AREA)/top_dir; => dir to run sims
   master_submission_policy : execute_locally;
   drm    : lsf;
   default_dispatch_parameters: <text>-q regress -We 00:30 -R "select[ws60 && CCASE && mem>2000]" -o /dev/null -e /dev/null -u /dev/null</text>; => lsf parameters
   max_runs_in_parallel     : 1000;
   queuing_policy : round_robin;
};

group smoke { //there can be multiple groups with each group having separate tests to run
   runs_dispatch_parameters:<text>-q regress -We 04:00 -R "select[ws60 && CCASE && mem>2000]"  -o /dev/null -e /dev/null -u /dev/null </text>;
   sve_name : "$ENV(DVWORK)/software/rtl_sim/regress.sve";
   run_script: "$ENV(DVWORK)/software/rtl_sim/run_regress.csh"; => calls this run script which has irun cmd
   scan_script: "vm_scan.pl `vm_root -home`/bin/ius.flt `vm_root -home`/bin/uvm.flt"; //this is scan script that scans for errors  (*E) in log files, and reports them. provided by cadence. To have your own filtering for errors, provide your own filter file, i.e custom.flt which has these lines:
                add_filter ("error", 5, "ERROR:",failure(1,"ICS", "FAILED", "FAILED", "$ENV{BRUN_TEST_NAME} FAILED due to 'ERROR' in logs")); //This si to filter out ERROR from log file
   sv_seed: gen_random; //use random seed for svseed parameter on irun
   timeout : 200000; //timeout a test after 200K sec
   count : 1;
   #include "veridian_tests.vsif" => has a lit of tests (doesn't need to be vsif file). #include is needed (C pgm syntax for including files)
};
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Above file calls "run_regress.csh" which is the run script which has irun cmd. This script has "$BRUN_TEST_NAME" in place of testcase name in irun cmd line, so that test names get picked up from *_tests.vsif file
It also has include file for other vsif file which has list of tests with args:
veridian_tests.vsif:
------
test efuse_t1 { count: 5 }; => test to be run 5 times with 5 random seed (and no additional args)
test efuse_jtag {
     sim_args : ahb_bfm;
     test_dir : efuse;
     test_def : DISABLE_DAP_SW_BFM;
};
test pwr_smoke {
     sim_args : ahb_bfm;
     test_dir : pwr_if;
};
#include "veridian_other_tests.vsif" => can include other vsif files too
---------------

top vsif file is called by emanager and starts running regression. It saves results in *.vsof file, which can be loaded later to see the results of regression. This is helpful when we want to reopen the window later.

#to run regression from cmd line, do this:
emanager -c "start_session -vsif /vobs/../veridian_regress.vsif

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vPlan:
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To create/update vplan, click on vPlan icon (right before Config icon). That will bring new vPlan window.
To create new vplan, click on "New", while to read existing vPlan click on "Read".
vplan file looks like xml file. It is easy to read it in emanager, but difficult to read text.

For new vPlan, on the new window, edit Plan name on vplan editor on left to something meaningful like "refsys dv". Then goto specs on right, and "add a spec". As as many spec files (im pdf) that you want. Highlight the section, that you want to be added, right click and choose "New section (sibling or child=> child will create sub section within that test, i.e 1.1->1.1.1)". Put a name, and then it shows that item on vplan editor on left.  Now if you click on "Plan" (by side of spec), then it shows attributes for each testcase that you added (if you click on that testcase). You can add "implementation notes" here to show what the testcase does. Once done, save file by going to File->Save as "refsys.vPlan".

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