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Published: Wednesday, 20 February 2019 20:35
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Design Reliability:

In chips, we have transistors and wires connecting them. They need to be functioning for 10 yrs or so. We run simulations to account for aging of transstors and wires.

BEOL=Back end of Line (metals and Vias),

FEOL = Front end of Line (transistors, everything below contact)

Transistor reliability: We measure many of these parameter affect for 10 yrs or 10K hrs of operation. FIT (failure in Time) rates are based on 10yrs of operation, so

  1. CHC: channel hot carrier: affects Transistor VT
  2. BTI: Bias Temperature instability: It degrades VT of Transistor during "ON" state at high temperature. It affects both NMOS and PMOS, though PMOS is affected more (reduces VT for NMOS, increases VT for PMOS => weaker tran).BTI happens when tran is ON, but starts fixing itself once tran is off.
    1. So, there are 2 BTI phase:
      1. Stress phase: here tran is ON, gate bias is max, causing max VT shift
      2. Relaxation phase: here tran is OFF, gate bias is min, reversing VT shift caused by stress phase. It's able to recover 20% of the VT shift caused by Stress phase. So, only 80% degradation of VT remains after Relaxation phase.
    2. Comparing BTI across tech:
      1. 180nm device => For PMOS which is contantly ON for 100K hrs @105C, with Vgs=1.8V, ΔVT = 10mv. 10mV is acceptable since there's already enough margin built into design.
      2. 10nm FinFet device => for NMOS, it's about 10mv, and PMOS is 50mv (assuming worst case 100% ON). At 1V applied across src/drn for 1nm device, Field is 1V/nm => 1KV/um, enough to break Si and SiO2 atoms. Better PBTI for finfet. NMOS BTI
    3. 2 kinds of BTI (-ve and +ve):
      1.  A. NBTI: -ve BTI, VT goes down. Here gate is at lower voltage than src, drn and subs. For tran to remain ON, this can only happen for PMOS. It is dominated by substrate interface traps. It's more severe than PBTI.
      2. B. PBTI: +ve BTI. VT goes up. Here gate is at higher voltage than src, drn and subs. For tran to remain ON, this can only happen for NMOS.  It is dominated by bulk HK trapped charges
  3.  HCI: same as CHC? FinFet HCI very challenging
  4. Self Heating: worse in Finfet as compared to planar, as fins surrounded by oxide.
  5. SEU : soft error vulnebility in srm cells, logic.
  6. ESD: ESD needed to protect gate oxide. In Finfet, Gate oxide breakdown is lower, and breakdown voltage of devices is also lower (=> FF more fragile). So, equiv ESD requires more area, bigger ESD devices.

 

Few more reliability notes:

 

  • Effective VT degradation = CHC + BTI
  • OverDrive capacity of Tran (i.e how much over voltage can they tolerate): For tran aging, stress voltages applied beyond rated voltages (1 V=rated voltage for 10nm NMOS/PMOS, stress voltage =1.2V), and higher temperatures. That's why thin oxide tran not used in IO. We make 2D plot of Voltage and temperature, and check the lifetime of tran, as well as VT shift of tran. We see that higher Voltage (30% higher than rated Voltage, so 1V rated tran stressed to 1.3V) and Higher Temp (> 50C), reduces lifetime of tran to couple of days. Very high voltages of >1.5V and Temp > 50C start causing VT shifts of 50mv or more (else it remains < 10mv). So, to assess Over Drive capability w/o getting the effect of VT shift, experiments limited to 30% voltage overdrive with Temp 50C.
  • HTOL stress (high temp operating life): High vol, high temp for 12-24 hrs gets same effect as aging.

 

 

Wire reliability:

Wires/Vias may suffer from reliability too. They may develop open/shorts due to multiple reasons.

  1. EM: lectro migration: Iavg/Irms/Ipeak calc.
  2. Self heating: happens for wires too.