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Published: Thursday, 31 August 2023 23:38

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Cortex M0+, M1, M3, M4, M7

These are all built as supersets of M0. They keep adding more hardware, support more instructions, more debug support, and hence resulting in larger size and higher power. The only exception is M0+ which is actually smallest microcontroller of all of M0 family.

Cortex M0+ (ARMv6-M):

Cortex M0+ is an optimized superset of the Cortex-M0, and is still based on ARMv6-M. The Cortex-M0+ has complete instruction set compatibility with the Cortex-M0 thus allowing the use of the same compiler and debug tools (so compilers etc still refer to arch as Cortex-M0) . The Cortex-M0+ pipeline was reduced from 3 to 2 stages, which lowers the power usage. In addition to debug features in the existing Cortex-M0, a silicon option can be added to the Cortex-M0+ called the Micro Trace Buffer (MTB) which provides a simple instruction trace buffer. The Cortex-M0+ also received Cortex-M3 and Cortex-M4 features, which can be added as silicon options, such as the Memory Protection unit (MPU) and the vector table relocation.

Cortex M1 (ARMv6-M):

The Cortex-M1 is an optimized core especially designed to be loaded into FPGA chips, and is still based on ARMv6-M. It brought back the 3 stage pipeline to improve performance.

Cortex M3 (ARMv7-M):

The Cortex-M3 is the first M processor based on ARMv7-M arch. It supports entire Thumbs1 and Thumbs2 ISA.

Cortex M4/M4F (ARMv7E-M):

Conceptually the Cortex-M4 is a Cortex-M3 plus DSP instructions, and optional floating-point unit (FPU). A core with an FPU is known as Cortex-M4F. It's based on ARMv7-M arch (or to be precise Enhanced version of v7 known as v7E)

Cortex M7/M7F (ARMv7E-M):

The Cortex-M7 is a high-performance core with almost double the power efficiency of the older Cortex-M4. It is like a modern processor featuring a 6-stage superscalar pipeline with branch prediction. A core with an FPU is known as Cortex-M7F. and is capable of single-precision and optionally double precision operations. The instruction and data buses have been enlarged to 64-bit wide over the previous 32-bit buses.