- Details
- Published: Friday, 12 October 2018 04:33
- Hits: 595
PDK (Process delivery kit) link: http://pdk.dal.design.ti.com/ (at Ti, we have pdk dir, which is used by our flow. All pdk info is kept in PCD (Process Control doc) for each process. Strawman PCD is built on simulated/extracted data (no Si data), Beta PCD is after the process baseline has been set and Production PCD is after verifying it with Si.
OA (open Access) PDK is now being used everywhere, which has database in OA format. OA format and API is developed by Si2 (Si2.org) and is free and open to everyone.
Mentor (process tech info) website: https://mentor.itg.ti.com
----------
FreePDK (from NCSU): base kit - http://www.eda.ncsu.edu/wiki/FreePDK
FreePDK (from Nangate): generic open cell lib based on 45nm.
Free CAD tools are here: http://opencircuitdesign.com/index.html
------------------
Scribe Line Structures: Test structures needed to verify the PCD.
-------
manufacturing grid : The manufacturing grid is the grid on which all design-rules are based. No shape may exist in the database that is not aligned to this grid. The manufacturing grid is 2.5 nm for this 45nm process on FreePDK45. Higher the MG, lower the cost of mask tooling.
LBC7: For TI LBC7 process, MG is 0.050 um, even though min coding increment of 0.10um is required. This is to accommodate centerpoint and centerline figures. Sizes that are not on grid, are snapped to nearest grid. final mask size adjust is a combination of the design size adjust, which adjusts sizing relative to the minimum grid size, the selective size adjust, and the process size adjust which compensates for process manufacturing offsets, amd may be different for different layers. A shrink of 0.9 is done from the Drawn CD to the final Reticle (mask) CD for LBC7.
------------------------
CDB PDK Dir: This has all lib data (schematic, layout, etc) in cadence database (cdb) format.
-----------
/db/pdk/<Process_name> (Process_name can be for fab process, packaging, foundry, etc)
lbc*/tsmc*/umc* => all fab process
bicom* => all bicmos info
foundary =>
sample_pdk =>
copper => metal/via rules put seprately here, since metal rules not mainatined by lbc7,etc process platform.
packagaing => all pkg rules here, since pkg rules not mainatined by lbc7,etc process platform.
--------
Most used Process_name : lbc7, lbc8(shrinking factor of 0.35 applied to drawn design for lbc8), tsmc*, umc*, bicom*
LBC7 dir: /db/pdk/lbc7/rev1/
DIGITAL LIB section
--------------------
digital lib dir: diglib/msl270/r3.0.0/. In this we have following dir:
verilog dir: all verilog models here
------------
verilog/models/*.v: models for all stdcells in terms of verilog primitives (nand, or, not, pullup, etc). It has also defines for TI_functiononly, TI_openhdl, etc.
For ex: AN210.v has the gate modeled as:
and #0 TI_AND_PRIM0 ( Y , A , B ) ; //Verilog Structure section (in terms of gate prims). and gate has 0 unit delay. we define gate delay as 0 and delay mode as "distributed" and timescale as 1ps in TI_functiononly mode, so that delays are added for each gate in ps. This doesn't affect much as delays are already 0, so total delay is also close to 0ps. However for non function mode, we define module delay as #ns, and set delay mode to "path" delay so that module delays are used directly. In non function mode, we define AN210 gate delay as #0.01 (equals 0.01ns with 1ns timescale directive). However, from ATD page, this gate has delay of about 1ns. So, delay not defined correctly. Doesn't matter as we don not use this delay value. We use the delay that comes directly from the gate delay in sdf file.
For delay cells (as DLY03), we model delay as 3 time unit delay (3ns for 1ns timescale).
For filler cells (as SPAREPOLYCAP32), we don't have anything in module defn.
verilog/verilogsrc(ams)/msl270_lbc7_*pin/*.vams : verilog analog models for all std cells. (4 variations of same cell: 2pin, 3pin, iso_2pin, iso_3pin). Note this wasn't there for normal verilog models as they don't model this variation in structure. 2 pin has VDd/VSS pins. 3pin and iso_2pin has additional PBKG pin. iso_3pin has further additional VSS_ISO pin.
Ex: AN210.vams => has 2 extra pins VDD,VSS as electrical pins (has additional PBKG pin for 3pin variation), and A,B,Y have sensitivity to VDD/VSS. rest of the structure section is same.
synopsys dir: all CORE.lib and CTS.lib here (same for all 4 variations of std cells)
--------------
synopsys/src/MSL270_*.lib: src lib files for various PVT corners for both CORE and CTS
synopsys/bin/MSL270_*.lib: binary .db files for various PVT corners for both CORE and CTS (derived from .lib files)
vdio dir: all lef and cap/res files
---------
vdio/lef/msl270_lbc7_tech*.lef: tech lef file. has metal/via width/spacing/antenna_ratio info. Diff tech files for 2/3/4 layer
vdio/lef/msl270_lbc7_core_*pin.lef: std cell lef files for all 4 variations (2pin, 3pin, iso_2pin, iso_3pin). For each std cell, lef file has physical metal layout info for i/p, o/p pins and VDD/VSS and/or BLKG/VSS_ISO. This doesn't have internal guts of cell, but just the pin and blkg info needed for routing.
vdio/captabl/2lm_maxC_maxvia.capTbl: use these LUT values for calc timing, instead of doing full extraction using Maxwell's eqn. defined for 2/3/4 metal layers for max/nom/min Cap/Res. has Cap table (which has cap values for diff width/space for diff metal layers), and various metal/via process variations (min Width/Space, height, thickness, resistance, thermal coeff,etc)
variation dir: all cdb data for all stdcells (schematic, symbol, layout, verilog)
--------------
msl270_lbc7_2pin/<std_cell>/layout|schematic|symbol|verilog|srcVerilog|srcVerilogAMS : similarly for iso_2pin, 3pin and iso_3pin. => note: schematic dir has sch.cdb and master.tag(master.tag just has sch.cdb written in it), layout dir has layout.cdb and master.tag((master.tag just has layout.cdb written in it), etc. everything is stored as cdb(cadence data base).
PAL dir: gdsii data for all stdcells kept here
-------
PAL/pml30CorePall/CORE/gdsii/CORE.fram.gdsii => for CORE cells
PAL/pml30CorePall/CTS/gdsii/CTS.fram.gdsii => for CTS cells
ANALOG DIR section
-----------------
drc rules: rules/assura/2010.12.22/
Assura is physical verification tool (both lvs/drc) from cadence. Its integrated with extraction tools.
drc.releaseNotes.txt => find all info related to drc files (drc rules are usually in drc.rul file, which incudes files from "files" dir).
copper rules are in /db/pdk/copper/rev1/rules/assura/*
packaging checks are in /db/pdk/packaging/rev1/rules/assura/*
qrc/ => has qrc tech files (in binary format) for metal/via layers.
QRC is 3D full-chip parasitic extraction and analysis tool from cadence. it includes an integrated field solver and does an RLCK extraction for cells, RF, analog, mixed signal, custom digital, etc.
------------------------
OA PDK Dir: This has all lib data (schematic, layout, etc) in open access database (oa) format.
-----------
/db/pdk/<Process_name>/<rev>/
Let's look at lbc8 dir: /db/pdkoa/lbc8/2011.06.26/
In this, we have following dir:
cdk/ copper/ diglib/ esdlib/ models/ releaseNotes/ rules/
DIGITAL LIB section for diglib dir:
--------------------
digital lib dir: diglib/pml30/. In this we have following dir:
verilog dir: all verilog models here, same as in CDB PDK.
synopsys dir: all CORE.lib and CTS.lib here. same as in CDB PDK.
vdio dir: all lef and cap/res files. same as in CDB PDK.
PAL dir: gdsii data for all stdcells kept here. same as in CDB PDK.
OA db dir: all OA data for all stdcells (schematic, symbol, layout, verilog)
ex: pml30_lbc8_2pin/BU110/ has following subdir:
*.oa contains actual data in oa format, while master.tag is ascii file with just the name of oa file that contains data. NOTE: even .oa files are not large, as they just have references to transistor, vias, metal lines, etc and don't contain the actual drawing.
schematic: sch.oa, master.tag, data.dm
symbol: symbol.oa, master.tag
layout: layout.oa, master.tag
abstract: layout.oa, master.tag => similar to layout dir, but is slightly smaller in size.
module, srcVerilog, srcVerilogAMS: all these dir have same content => netlist.oa, master.tag, verilog.vams.
-------------------------------------------